SRAM Power Saving Module Using Word Line Signals
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Solution Overview
Problem
Conventional SRAM designs face challenges in reducing leakage current while maintaining a minimum power supply voltage and minimizing silicon real estate, as existing power saving controllers are large and do not discriminate between selected and unselected cells.
Innovation Solution
An SRAM device with a power saving module activated by word line signals, which includes a latch unit, pass gate transistors, and a power saving module that raises the source voltage of the latch unit in response to a control signal on the word line, reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the minimum voltage Vccmin of power supply is raised to ensure proper SRAM function, then the SRAM device functions properly, but the layout area increases and leakage current increases
Solution Approach 1:
The patent divides the SRAM bank into multiple segments (banks) and applies power saving control independently to each bank. The power saving controller is segmented to control individual banks rather than the entire SRAM array, allowing selective activation of power saving mode in unselected banks while maintaining normal operation in selected banks. This segmentation reduces the overall area required for power saving circuitry compared to cell-level control.
Solution Approach 2:
The patent applies different voltage conditions to different regions of the SRAM array. Selected banks maintain normal Vcc voltage for proper operation, while unselected banks have their source nodes raised to reduce leakage current. This local differentiation allows the system to optimize for both functionality and power saving in different spatial regions simultaneously.
2Object-generated harmful factors
If the conventional power saving controller is designed to reduce leakage current for all cells in the bank, then leakage current is reduced, but the controller size increases and occupies excessive silicon real estate
Solution Approach 1:
The power saving controller is divided into multiple independent control units, each responsible for controlling a specific bank of SRAM cells. Instead of requiring one large controller to manage all cells in the array, each bank has its own dedicated control unit that manages only the source nodes within that bank. This segmentation dramatically reduces the total controller area while maintaining effective leakage current reduction across all banks.
Solution Approach 2:
The patent applies power saving control only to unselected banks rather than all banks simultaneously. When a bank is selected for read/write operations, its power saving control is deactivated to maintain normal operation. This partial application of power saving control reduces the active controller area needed at any given time, as controller units for selected banks can be in a low-power or inactive state.
3Object-generated harmful factors
If the conventional power saving controller controls an entire bank without discrimination, then leakage current is reduced for all cells, but unselected cells do not receive optimal leakage reduction and selected cells cannot perform read/write operations
Solution Approach 1:
The SRAM array is divided into multiple independently controllable banks, each with its own power saving control unit. This segmentation enables selective activation of power saving mode in specific banks while maintaining normal read/write operations in other banks. The fine-grained control at the bank level allows the system to optimize leakage reduction without compromising operational versatility.
Solution Approach 2:
The power saving control system is made dynamic by continuously monitoring bank selection status and adjusting the control state accordingly. When a bank is selected for operations, its power saving control is dynamically deactivated; when unselected, it is dynamically activated. This dynamic adaptation allows the system to seamlessly switch between power saving and operational modes, maintaining both leakage reduction effectiveness and operational versatility.
Data Source
AI summary
An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.