Semiconductor Device Time-Sharing Inter-Chip Wiring Ising Model Simulation
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Solution Overview
Problem
The challenge lies in developing a semiconductor device that can simulate interactions between nodes of a large-scale Ising model at a low manufacturing cost, as existing solutions require numerous element units, leading to high chip sizes and increased manufacturing costs due to extensive wiring between semiconductor chips.
Innovation Solution
A semiconductor device comprising multiple chips connected by an inter-chip wire, where each chip simulates interactions between nodes and shares communication via time-sharing to reduce wiring complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are connected to simulate large-scale Ising models, then the simulation capability is improved, but the amount of inter-chip wiring increases leading to higher manufacturing costs
Solution Approach 1:
The patent divides the large-scale Ising model simulation into multiple semiconductor chips, where each chip handles a subset of nodes. This segmentation allows the system to achieve large-scale simulation capability while managing wiring complexity by limiting connections to only necessary inter-chip communications rather than full mesh connectivity.
Solution Approach 2:
The patent extracts and eliminates unnecessary wiring connections between chips by implementing a sparse connection topology. Only essential inter-chip wires are established to transmit necessary data, removing redundant connections and thereby reducing manufacturing cost while preserving simulation functionality.
2Measurement precision
If numerous element units are used to simulate interactions, then the accuracy of simulation is improved, but the chip size increases leading to higher manufacturing costs
Solution Approach 1:
The patent segments the simulation nodes across multiple chips rather than placing all element units on a single chip. This distribution maintains simulation accuracy by preserving the necessary number of element units while reducing the area requirement of each individual chip, thereby lowering manufacturing costs.
Solution Approach 2:
The patent transitions from a single-chip two-dimensional layout to a multi-chip three-dimensional architecture. By stacking or arranging multiple chips in space, the system accommodates numerous element units without increasing the footprint of any single chip, thus maintaining accuracy while controlling manufacturing cost.
Data Source
AI summary
A semiconductor device is provided with a plurality of semiconductor chips, each of which simulates interactions between nodes of an interaction model, and an inter-chip wire, wherein the plurality of semiconductor chips are used to simulate interactions between nodes of a single interaction model; each semiconductor chip includes a connection unit that sends and receives some of the values indicating the state of the nodes, which are retained by a necessary element unit, via inter-chip wire to and from another semiconductor chip or sends and receives the values indicating state of the nodes, which are retained by the necessary element unit to and from the other semiconductor chip while sharing the inter-chip wire by means of time sharing.