8T SRAM Cell Two-Phase Write Scheme Low Voltage Operation
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Solution Overview
Problem
Existing SRAM designs face challenges in achieving 100% writability, hold stability, and read-stability at low voltages while minimizing power consumption and area, especially in bit-interleaved architectures, where write assist circuits consume extra power and degrade reliability.
Innovation Solution
A two-phase sequential write scheme for SRAM memory cells using an 8T architecture without assist techniques, where write '0' and write '1' operations are performed in sequential phases with guard time windows, ensuring stability of half-selected cells by pre-charging bit-lines to opposite values, thus avoiding conflicts between pass-gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write assist circuits are used to improve write ability at low voltage, then write margin is improved, but power consumption and area increase
Solution Approach 1:
The patent removes write assist circuits from the SRAM architecture, achieving low-voltage operation without the additional power consumption and area overhead that assist circuits would introduce. The core invention demonstrates that proper bit-cell design and write scheme can achieve write ability at low voltage without external assistance.
Solution Approach 2:
The patent changes the operating voltage parameter to achieve low-voltage operation (near threshold voltage) while maintaining write ability through optimized pass-gate design and write scheme, eliminating the need for voltage boosting circuits that would consume additional power.
2Reliability
If word-line boost and negative bit-line techniques are used to operate at lower voltages, then write ability is improved, but excessive gate to source voltage degrades reliability and lowers SNM
Solution Approach 1:
The patent pre-charges bit-lines to opposite values before write operations and uses sequential phase control to prepare the bit-cell state in advance, eliminating the need for excessive voltage boosting that would create harmful electrical stress on pass gates during write operations.
3Reliability
If bit-interleaving is used to reduce multiple event upsets, then reliability against MEUs is improved, but hold stability of half-selected cells deteriorates
Solution Approach 1:
The patent segments the write operation into two sequential phases with guard time windows, where each phase targets specific bit-cells. This segmentation allows bit-interleaved architecture to maintain MEU resistance while preserving hold stability through controlled sequential access that prevents conflicting write operations on half-selected cells.
Solution Approach 2:
The patent uses periodic alternating phases for writing different data values to interleaved bit-cells, with guard time windows between phases. This periodic action ensures that half-selected cells remain stable while maintaining the benefits of bit-interleaving against multiple event upsets.
4Area of stationary object
If two switches are used in series in pass-gate for higher density, then area is reduced, but write ability deteriorates
Solution Approach 1:
The patent dynamically controls the two series pass-gate switches using sequential phase signals, enabling one switch to be fully ON while the other is controlled during write operations. This dynamic control compensates for the series connection degradation and maintains write ability while achieving high density through the compact two-switch design.
Data Source
AI summary
An SRAM cell in a bit interleaved memory architecture with two phase sequential write scheme to achieve 100% write ability and the SNM target with bit interleaved architecture in SRAM.