Symmetrical Memory Read Circuit for Temperature-Stable Bit-Line Sensing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increase in length of bit lines in variable-resistance memory leads to subthreshold leakage currents, which are affected by temperature, causing inconsistent read reference current windows and reduced reading accuracy of stored values at different temperatures.

Innovation Solution

A read circuit design with structurally symmetrical arrays and dual current comparison sub-circuits to offset subthreshold leakage currents, ensuring accurate reading by adjusting resistance values and using symmetrical bit lines to stabilize current comparisons.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the length of bit line is increased to accommodate more storage bits, then the storage capacity is improved, but the subthreshold leakage current accumulation increases causing reduced reading accuracy

Engineering Contradiction:
Improvestorage capacityVSAvoidreading accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The bit line is divided into two separate bit lines (first bit line and second bit line), each carrying current from different sets of storage bits. This segmentation reduces the accumulation of subthreshold leakage current on each individual bit line, thereby improving reading accuracy while maintaining high storage capacity through the expanded array structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A current mirror circuit is introduced to create a copy of the reference current. This copied current is used to compensate for the subthreshold leakage current effects, allowing the system to maintain accurate readings even as bit line length increases to accommodate more storage bits.

Inventive Principle:
Principle #26Copying

2Device complexity

If the preset reference current is fixed to simplify the reading mechanism, then the device complexity is reduced, but the reading accuracy deteriorates under temperature variations

Engineering Contradiction:
Improvereading mechanism complexityVSAvoidreading accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The reference current is made dynamically adjustable based on temperature conditions rather than being fixed. The current mirror circuit allows the reference current to be modified in response to temperature variations, compensating for the temperature-dependent characteristics of subthreshold leakage current and maintaining reading accuracy across different temperature environments.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution stabilizes read reference current windows across varying temperatures, ensuring consistent reading accuracy of stored values in variable-resistance memory.

Implementation Method 1

The varistor is configured to store binary bits. A high-resistance state of the varistor indicates that a stored value is a binary bit '1', and a low-resistance state of the varistor indicates that a stored value is a binary bit '0'.

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Implementation Method 2

If the obtained current is less than the preset reference current, it indicates that the selected storage bit on the BL is in a high-resistance state

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Implementation Method 3

The MOS switching tube is configured to select a storage bit. The switching state of the MOS switching tubes in the storage bits can be controlled by the WL

Methodology Applied
Scientific EffectMOS Field Effect:

Implementation Method 4

subthreshold leakage currents (trace leakage currents between sources and drains when the MOS switching tubes are in a shutdown region) exist on these MOS switching tubes

Methodology Applied
Scientific EffectSubthreshold Leakage:

Data Source

PatentUS12518804B2Memory and read circuit thereof
Publication Date: 2026.01.06 ZHEJIANG HIKSTOR TECHOGY CO LTD
  • US12518804B2 patent drawing
  • US12518804B2 patent drawing
  • US12518804B2 patent drawing

AI summary

Disclosed are a memory and a read circuit thereof. The memory includes a plurality of storage arrays, where each storage array includes a first array and a second array structurally symmetrical to the first array. The read circuit of the memory includes a plurality of bit read circuits corresponding one-to-one to the plurality of storage arrays, where each bit read circuit includes a word line control circuit, a bit line control circuit and a current comparison circuit.