Voltage Control Circuit for Phase-Change Memory Writing
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Solution Overview
Problem
Phase-change memory (PCM) and interfacial PCM (iPCM) require a slow cooling operation to reliably switch between set and reset states, as rapid voltage sinking can result in unstable state transitions, necessitating a configuration to control the rate at which voltage is sunk on bit lines during data writing.
Innovation Solution
A semiconductor storage device with a voltage control circuit that adjusts the sinking rate of the voltage on selected bit lines using a sink circuit and current supply circuit, allowing for precise control of the slow cooling operation by adjusting the sink current and current supply paths to ensure reliable writing of set and reset states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is rapidly sunk on bit lines during data writing, then writing speed is improved, but state transition reliability deteriorates
Solution Approach 1:
The patent applies dynamics by making the voltage sinking rate adjustable rather than fixed. The sink circuit can dynamically change the sinking rate based on the required operation mode (set or reset), allowing fast sinking when reliability is less critical and slow sinking when state transition reliability is paramount. This resolves the contradiction by making speed adaptable to reliability requirements.
Solution Approach 2:
The patent changes the parameter of voltage sinking rate from a constant value to a variable parameter that can be adjusted between fast and slow rates. By controlling the sink current magnitude, the system can switch between rapid voltage sinking (for speed) and controlled voltage sinking (for reliability), thus resolving the technical contradiction between writing speed and state transition reliability.
2Reliability
If slow cooling operation is implemented to ensure reliable state transitions, then state transition reliability is improved, but writing speed deteriorates
Solution Approach 1:
The system dynamically adjusts the voltage sinking rate based on the specific writing operation needed. For set operations requiring reliable state transitions, the sink circuit operates in slow cooling mode. For operations where speed is more critical, the system can use faster sinking rates. This dynamic adaptation resolves the contradiction by making reliability and speed complementary rather than opposing.
Solution Approach 2:
The patent implements periodic action through multi-stage voltage sinking operations. The system can alternate between fast sinking phases (for speed) and slow cooling phases (for reliability) in a controlled sequence, allowing both requirements to be satisfied at different stages of the writing process.
3Reliability
If voltage sinking rate is controlled to ensure stable state transitions, then data storage reliability is improved, but current consumption increases
Solution Approach 1:
The patent changes the voltage sinking rate parameter to be adjustable rather than fixed at a conservative slow rate. By optimizing the sinking rate parameter for each specific operation, the system achieves reliable state transitions without unnecessarily slow operations that would increase current consumption. The parameter is tuned to the minimum required rate for reliability, reducing wasted energy.
Solution Approach 2:
The system applies partial slow cooling action only when and where needed for reliable state transitions, rather than always using the slowest possible sinking rate. This partial application of slow cooling ensures reliability for critical transitions while maintaining faster, lower-current operations for less critical cases, thus reducing overall current consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and efficient writing of data in PCM and iPCM by controlling the voltage sinking rate, stabilizing state transitions and reducing current consumption, thus improving data storage reliability and efficiency.
Implementation Method 1
the PCM and the iPCM are brought to a low resistance state (a set state) or a high resistance state (a reset state) according to phase transition of a phase-change film
Implementation Method 2
an operation called 'slow cooling' of slowly sinking a voltage applied to the memory cell is required
Data Source
AI summary
A semiconductor storage device according to an embodiment includes a plurality of resistance-change storage elements. A plurality of bit lines are connected to the storage elements, respectively. A voltage control circuit controls a decreasing rate of an absolute value of a voltage of a selected bit line among the bit lines when data is written to one of the storage elements.