3D Memory Cell Stack Layout With Shared Word Line Pads
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the area occupied by memory cells, hindering the development of higher-capacity devices.
Innovation Solution
A three-dimensional semiconductor memory device is designed with memory cells stacked in a vertical direction, featuring alternating stack and pad regions, word lines and bit lines arranged in specific horizontal and vertical directions, and shared bit lines between adjacent sub-cell arrays, along with sub-word line drivers to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory cells are arranged in two dimensions, then the device structure is simple, but the integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking, where multiple memory cell layers are vertically stacked above the substrate. This dimensional change allows integration density to increase without proportionally increasing the horizontal footprint, thereby resolving the contradiction between simple device structure and limited integration density.
2Reliability
If more word line pads and contacts are used, then electrical connection is improved, but the area occupied by pad regions increases
Solution Approach 1:
The patent merges multiple word line pads and contacts into shared pad structures. Specifically, multiple word lines from different memory cell layers are connected to common word line pads through shared contact structures, reducing the total number of discrete pads and contacts required. This merging maintains reliable electrical connections while minimizing the area occupied by pad regions.
Solution Approach 2:
The word line pads and contact structures are designed to serve multiple functions simultaneously. A single word line pad structure provides electrical connection to multiple word lines across different memory cell layers, making the pad structure universal rather than dedicated to a single word line. This multi-functionality reduces the overall pad region area while maintaining comprehensive electrical connectivity.
3Ease of manufacture
If pad regions are enlarged, then manufacturing is easier, but the memory cell density is reduced
Solution Approach 1:
By stacking memory cell layers vertically in the third dimension, the patent increases memory cell density without requiring proportional enlargement of horizontal pad regions. The vertical stacking allows more memory cells to be packed into the same footprint area, thereby increasing density while keeping pad regions at manageable sizes that remain manufacturable.
Solution Approach 2:
The shared pad structures combine multiple electrical connections into unified pad regions, reducing the total pad area required compared to having separate pads for each word line. This merging creates larger, fewer pad structures that are easier to manufacture while leaving more area available for high-density memory cell stacking.
Data Source
AI summary
A semiconductor memory device may include a substrate including a stack region and a pad region in a first horizontal direction, word lines extending in the first horizontal direction in the stack region, bit lines extending in a vertical direction in the stack region and spaced apart from one another in the first horizontal direction and a second horizontal direction, memory cells in the stack region and between the word lines and the bit lines, and a pad structure including word line pads spaced apart from each other in the vertical direction in the pad region. The word lines may include first and second word lines, which may be separated from each other in the second horizontal direction. The first and second horizontal directions may different. Each of the word line pads may be connected to the first and second words lines at a same vertical level.