Reference Bit Line Stabilizes Read Accuracy in Stacked Memory
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Solution Overview
Problem
Current stacked memory devices face challenges in achieving high accuracy during read operations due to limitations in the integration and configuration of source-drain and gate structure bodies, which affect the precision of bit line and word line connections.
Innovation Solution
The memory device incorporates a specific configuration of source-drain and gate structure bodies with bit lines, semiconductor layers, and charge storage films, along with a method for manufacturing that includes forming global word lines using a sidewall double patterning process, enhancing the accuracy of read operations by stabilizing the potential of reference bit lines and reducing gate leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional stacked memory device configuration is used, then device integration is achieved, but read operation accuracy is insufficient due to gate leakage currents and potential instability
Solution Approach 1:
A reference bit line is introduced as an intermediary element between the bit lines and the sense amplifier. This reference bit line is connected to local word lines through global word lines, allowing it to track and cancel out gate leakage currents that affect the memory cells. The reference bit line acts as a mediator that compensates for the harmful gate leakage effects without directly interfering with the data storage function.
Solution Approach 2:
The patent changes the electrical parameters of the system by introducing a dedicated reference bit line with specific connectivity patterns. The reference bit line is connected to alternating gate structure bodies through global word lines, creating a controlled electrical path that mirrors the leakage current paths of the memory cells. This parameter change enables the system to measure and compensate for leakage currents, improving read accuracy.
2Manufacturing precision
If more lithography steps are used to form global word lines, then manufacturing precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The formation of global word lines is merged with the existing local word line formation process. By using the same lithography masks and etching steps that define the local word lines, the global word lines are simultaneously formed without requiring additional lithography steps. This merging of processes maintains manufacturing precision while reducing overall process complexity.
Solution Approach 2:
The lithography masks and patterning processes are designed to serve multiple functions: they define both the local word lines and the global word lines in a single set of steps. The same mask patterns are used to create multiple functional elements, making the lithography process universal and eliminating the need for separate dedicated steps for global word line formation.
Data Source
AI summary
A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.