Shift Register Buffer Circuit Voltage Overlap Reduction
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Solution Overview
Problem
Conventional shift register circuits experience voltage overlap between output signals from adjacent units, leading to sampling errors when driving transistors with a 2-volt threshold voltage in LCDs, as the signals overlap, causing two transistors to turn on simultaneously.
Innovation Solution
A shift register circuit design that includes a shift register unit composed of two inverters and four transistors, along with a buffer composed of four additional transistors, which introduces a delay between output signals from two shift register units to minimize voltage overlap, preventing simultaneous activation of connected transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional shift register units are used without additional buffering, then the circuit complexity is low, but voltage overlap between adjacent output signals causes sampling errors
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between adjacent shift register units. This buffer delays the output signal from one shift register unit, creating a time separation that prevents voltage overlap with signals from adjacent units. The buffer acts as a mediator that resolves the conflict between maintaining simple circuitry and achieving reliable sampling by introducing a controlled delay element.
2Reliability
If output signals from shift register units are transmitted without delay, then the sampling rate is high, but voltage overlap causes simultaneous transistor activation and sampling errors
Solution Approach 1:
The buffer introduces a partial delay that is sufficient to separate overlapping voltage signals but not excessive enough to significantly impact the overall sampling rate. The delay is carefully controlled to provide just enough time separation to prevent simultaneous transistor activation while maintaining high sampling efficiency. This partial action approach resolves the contradiction by applying only the necessary amount of delay.
3Reliability
If a buffer with four transistors is added to each shift register unit, then voltage overlap is minimized from 11V to 1.5V, but the device complexity increases
Solution Approach 1:
The buffer circuit changes the temporal parameter of the output signal by introducing a controlled delay. This parameter change in the signal timing transforms the overlapping voltage profiles into separated profiles, reducing the overlap from 11V to 1.5V. The parameter change approach resolves the contradiction by modifying the time characteristic of the signal rather than changing the fundamental circuit topology.
Data Source
AI summary
A shift register circuit includes a shift register unit and a buffer. The buffer is coupled to the output terminal of the shift register unit to delay the output signal from the shift register unit. The overlapped voltage of two output signals from two adjacent shift register units can be reduced.