Semiconductor Memory Bias Control for Leakage and Reliability
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Solution Overview
Problem
Semiconductor memory devices face challenges in adapting bias voltages to diverse operating conditions and environments, leading to reduced operating reliability and increased power consumption.
Innovation Solution
A semiconductor memory device with a memory cell area and peripheral circuit area stacked and overlapped in a direction, allowing for separate control of first and second bias voltages applied to transistors, optimizing threshold voltages and off-currents, and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant bias voltage is used to control transistors within a certain operating range, then the device structure is simple, but the device cannot adapt to diverse operating conditions and environments, reducing operating reliability
Solution Approach 1:
The patent divides the semiconductor device into two distinct regions: a memory cell area with first transistors receiving a first bias voltage, and a peripheral circuit area with second transistors receiving a second bias voltage. This segmentation allows each region to be optimized independently for its specific operating requirements, enabling adaptation to diverse operating conditions while maintaining reasonable structural organization.
Solution Approach 2:
The patent applies different bias voltages to different regions of the device. The memory cell area receives a first bias voltage optimized for memory operations, while the peripheral circuit area receives a second bias voltage optimized for circuit operations. This local quality approach allows each region to operate at optimal performance levels for its specific function, improving overall reliability without requiring complete redesign of the entire device.
2Adaptability or versatility
If separate bias voltages are applied to memory cell area and peripheral circuit area, then adaptability to operating conditions is improved, but device complexity increases
Solution Approach 1:
The device is segmented into a memory cell area and a peripheral circuit area, each with independent bias voltage control. This segmentation enables the memory cell area to be optimized for low-power memory operations while the peripheral circuit area can be optimized for high-speed circuit operations, achieving high adaptability to different operating conditions through regional optimization rather than complex global control.
Data Source
AI summary
A semiconductor memory device is provided which is capable of adaptively controlling bias and a method of operating the same. The semiconductor memory device includes: a memory cell area including a plurality of first transistors to which a first bias voltage is applied; and a peripheral circuit area which overlaps the memory cell area in a first direction and includes a plurality of second transistors to which a second bias voltage controlled differently from the first bias voltage is applied.