Memory Wake-Up Sequencing With Secondary Sleep Loop Control
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Solution Overview
Problem
Existing memory systems face challenges in managing power states, particularly during transitions from low power modes to active states, leading to high in-rush currents due to overlapping memory array power-up and bit line pre-charge operations, which fail to meet design criteria for reduced peak current during light sleep wake-up.
Innovation Solution
Implementing a secondary sleep loop in semiconductor memory systems to separate memory array power-up and bit line pre-charge operations, allowing for sequential and staggered power management, thereby reducing wake-up peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory array power-up and bit line pre-charge operations are performed simultaneously, then wake-up time is reduced, but in-rush current increases significantly
Solution Approach 1:
The patent segments the wake-up process into distinct phases: first completing memory array power-up, then separately completing bit line pre-charge operations. This temporal segmentation prevents simultaneous operation of power-up and pre-charge circuits, thereby reducing in-rush current while maintaining acceptable wake-up performance.
Solution Approach 2:
The patent implements preliminary action by completing the memory array power-up sequence before initiating the bit line pre-charge sequence. The power-up completion signal is used to enable the pre-charge operation only after the array is fully powered, ensuring that no in-rush current is generated during the transition.
2Device complexity
If a single sleep loop is used for power management, then device complexity is reduced, but peak current during wake-up cannot be sufficiently reduced
Solution Approach 1:
The patent divides the sleep loop into two separate loops: a first sleep loop for managing memory array power states and a second sleep loop for managing bit line pre-charge operations. This segmentation allows independent control of each phase, enabling peak current reduction while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the first sleep loop generates a power-up completion signal that dynamically enables the second sleep loop's pre-charge operations. This dynamic inter-loop control allows the system to adapt the timing and sequencing of power-up and pre-charge operations to minimize peak current while maintaining flexibility.
Data Source
AI summary
Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a first memory cell, a first buffer, first logic circuitry, and first switching circuitry. The first memory cell may be configured to pre-charge in response to receiving a primary sleep signal. The first buffer may be configured to receive the primary sleep signal, generate a delayed primary sleep signal, and provide the delayed primary sleep signal to a second memory cell. The first logic circuitry may be configured to generate a first bit line pre-charge signal for the first memory cell of the plurality of memory cells in response to a looped sleep signal, wherein the looped sleep signal is generated based on the delayed primary sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal.