Semiconductor Data Clock Phase Training for Read Margin Stability
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Solution Overview
Problem
The duty cycle of data clock signals in semiconductor devices fluctuates with varying temperatures and voltages, leading to degraded margins for data signal reading, especially at higher frequencies, necessitating an adjustment for accurate data transmission.
Innovation Solution
A semiconductor device with a data clock signal generator circuit that outputs multiple phases, a data transmitter that delays a test pattern, and a training circuit that adjusts delay values and codes to determine optimal duty cycle settings based on sampling data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the data clock signal is increased to achieve high-rate data transmission, then the data transmission rate is improved, but the duty cycle fluctuation becomes more significant and the reading margin is degraded
Solution Approach 1:
The patent performs duty cycle training before actual data transmission operations. The training circuit pre-adjusts the duty cycle of the data clock signal to an optimal value using a training pattern, so that when actual data transmission occurs at high frequencies, the clock signal already has the correct duty cycle to maintain adequate reading margins throughout the operational range.
Solution Approach 2:
The patent dynamically adjusts the duty cycle parameter of the data clock signal based on operating conditions. The training circuit varies the duty cycle parameter during training operations to identify the optimal value, and then maintains this optimized parameter setting during high-frequency data transmission to ensure both high productivity and reliable reading margins.
2Reliability
If the duty cycle of the data clock signal is adjusted to compensate for temperature and voltage variations, then the reading margin is improved, but additional training operations and complexity are introduced
Solution Approach 1:
The training circuit automatically performs duty cycle calibration without requiring external intervention or complex control systems. The circuit uses internal resources including the data clock signal generator, delay elements, and sampling circuitry to self-adjust the duty cycle parameter based on detected signal characteristics, thereby improving reading margins while minimizing added complexity.
Solution Approach 2:
The training circuit is designed to perform multiple functions: it generates training patterns, delays signals, samples the delayed signals, determines optimal duty cycle values, and applies the corrected duty cycle to the data clock signal. By consolidating these functions into a single multi-functional block, the patent improves reading margin reliability without proportionally increasing overall system complexity.
3Reliability
If multiple internal data clock signals with different phases are generated to improve sampling accuracy, then the data transmission reliability is improved, but the clock signal generator complexity increases
Solution Approach 1:
The patent divides the clock signal generation function into multiple phase-separated internal data clock signals. Instead of using a single complex adjustable clock, the system generates multiple simpler clock signals with fixed phase relationships (e.g., 0°, 90°, 180°, 270°). This segmentation allows the sampling circuit to select the most appropriate phase for current operating conditions, improving sampling accuracy while keeping each individual clock signal generator simple.
Data Source
AI summary
A semiconductor device includes: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.