3D Memory Array Dual-Gate Read Structure for IR Drop Relief
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Solution Overview
Problem
Existing three-dimensional memory arrays face challenges with significant voltage drops (IR drops) on read word lines, limiting the process length and hindering the development of large-capacity memory structures.
Innovation Solution
A three-dimensional memory array design featuring dual-gate transistors is implemented, where the read transistor is a dual-gate structure with one gate connected to the read word line, mitigating current flow through the gate during read operations, and the transistors are stacked in different metal layers, allowing for perpendicular stacking and reduced cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read transistor structure is used, then the current reading operation is simple, but a serious voltage drop (IR drop) occurs on the read word line, limiting the process length
Solution Approach 1:
The patent transitions from a planar transistor structure to a three-dimensional stacked structure. The read transistor is formed with source and drain regions extending in the vertical direction (stacking direction), allowing the channel to be positioned at different heights. This spatial reconfiguration reduces the current path length through the read word line, thereby minimizing IR drop while maintaining functional performance.
2Quantity of substance
If memory cells are arranged in a planar configuration, then the layout is simple, but the storage density is limited due to area constraints
Solution Approach 1:
The patent implements vertical stacking of memory cells in the stacking direction, transforming the conventional two-dimensional planar arrangement into a three-dimensional structure. Multiple memory cells are positioned at different heights along the vertical axis, allowing significant increase in storage capacity within the same planar footprint. This dimensional transition directly addresses the area constraint while maximizing storage density.
3Quantity of substance
If the process length of read word line is extended to increase storage capacity, then larger memory arrays can be formed, but the voltage drop (IR drop) becomes more serious
Solution Approach 1:
By stacking the read transistor vertically and positioning its channel at a different height from the source and drain regions, the patent creates a compact three-dimensional configuration. This reduces the horizontal extent required for the read word line connection, thereby limiting the process length and minimizing IR drop while still enabling large-capacity memory arrays through vertical expansion.
Data Source
AI summary
The present disclosure relates to three-dimensional memory arrays, memories, and electronic devices. Each memory cell in an example three-dimensional memory array includes a first transistor and a second transistor. The second transistor used as a read transistor may use a dual-gate structure. One gate is electrically connected to the first transistor used as a write transistor, and the other gate may be electrically connected to a read word line. One of a source and a drain of the second transistor is grounded. In addition, in a process structure of the memory cell, each film layer structure of the first transistor and each film layer structure of the second transistor are integrated into at least four stacked insulation dielectric layers.