SRAM Macro Assist Control for Low-Voltage DVFS Operation
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Solution Overview
Problem
Operating SRAMs at low voltages is challenging due to variations in characteristics, leading to increased power loss, decreased reading speed, and data destruction risks when power supply voltage is dynamically controlled, and existing solutions complicate chip design with complex wiring and limited circuit integration.
Innovation Solution
A semiconductor chip with SRAM macros that include a determination block to generate mode signals for adjusting read and write assist amounts based on power supply voltage, using a power supply voltage monitor and delay determination memory to dynamically control assist operations, preventing power loss and data destruction while reducing wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is dynamically controlled (DVFS), then power consumption can be reduced, but power loss increases, reading speed decreases, and data destruction risk increases when voltage is in high voltage range
Solution Approach 1:
The patent implements dynamic adjustment of read assist and write assist amounts based on the current power supply voltage level. The control circuit monitors voltage changes and dynamically modifies assist operation强度 to match the voltage state, ensuring reliable SRAM operation across the full DVFS range while preventing data destruction in high voltage states and maintaining adequate assist in low voltage states
Solution Approach 2:
The patent changes the parameters of read assist and write assist operations based on power supply voltage levels. By adjusting these assist parameters dynamically, the system adapts to different voltage conditions, preventing excessive assist (which causes data destruction) in high voltage ranges while providing sufficient assist in low voltage ranges
2Device complexity
If read assist and write assist amounts are designed to be proportional to power supply voltage, then circuit design is simplified, but power loss increases and reading speed decreases in high voltage range
Solution Approach 1:
The patent introduces feedback control where the control circuit monitors the actual power supply voltage level and adjusts the read assist and write assist amounts accordingly. This feedback mechanism replaces simple proportional design with intelligent adaptation, reducing power loss by preventing excessive assist operations in high voltage states while maintaining adequate performance
3Use of energy by moving object
If power supply voltage is lowered, then power consumption is reduced, but required read assist and write assist amounts increase
Solution Approach 1:
The patent dynamically adjusts assist operation强度 in response to power supply voltage changes. When voltage is lowered, the control circuit automatically increases read assist and write assist amounts to compensate for the reduced voltage headroom, ensuring reliable SRAM operation across the full voltage range
Data Source
AI summary
A plurality of SRAM macros each including a memory cell array, an input/output circuit, a word line driver, and a control circuit are mounted on a semiconductor chip. Each of the SRAM macros includes a determination block disposed in the control circuit and configured to generate a mode signal for determining a read assist amount and a write assist amount based on a power supply voltage of the SRAM macro, and an assist circuit that performs a read assist operation and a write assist operation based on the mode signal generated by the determination block.