3D Semiconductor Memory Grain Control via Carbon Layer
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive equipment required for fine pattern formation, making it difficult to increase memory density, while three-dimensional semiconductor memory devices aim to overcome this by arranging memory cells in a vertical structure.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a carbon-containing layer, alternately stacked electrode interlayer dielectric and electrode layers, and semiconductor patterns with smaller grain sizes, which penetrate the stack structure, enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are used to increase integration, then manufacturing cost increases due to expensive fine pattern equipment, but device density cannot be sufficiently increased
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing memory density to increase without requiring finer lateral patterning. This dimensional change enables higher integration while avoiding the need for expensive advanced lithography equipment.
2Quantity of substance
If grain size in semiconductor patterns is reduced to increase density, then manufacturing precision becomes more difficult to control, but memory density increases
Solution Approach 1:
The patent introduces a carbon-containing layer with specific carbon concentration (3-15 at%) to control the grain growth characteristics of the semiconductor pattern. By adjusting the carbon concentration parameter, the grain size is suppressed to a controlled range without requiring extremely precise patterning processes, thus achieving high density while maintaining manufacturability.
Solution Approach 2:
The patent uses a composite structure combining silicon-based semiconductor material with a carbon-containing layer. The carbon-containing layer acts as a grain growth suppressor, creating a composite material system where the carbon component controls the grain structure of the semiconductor pattern, enabling fine grain size control for high density.
3Reliability
If uniform grain size is not controlled, then reliability decreases due to worst on cell current issues, but manufacturing complexity is reduced
Solution Approach 1:
The patent controls the carbon concentration parameter in the carbon-containing layer to suppress grain growth and achieve uniform grain size distribution. This parameter control ensures that all memory cells have similar electrical characteristics, preventing worst on cell current issues and improving reliability without adding significant manufacturing complexity.
Solution Approach 2:
The carbon-containing layer serves as an intermediary substance between the substrate and the semiconductor pattern. It mediates the grain growth process, ensuring uniform grain formation in the semiconductor pattern. This intermediary layer simplifies the control of grain uniformity compared to direct patterning methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the reliability and uniformity of semiconductor memory devices by reducing grain size distribution and preventing issues like 'worst on cell current', thereby improving memory density and performance.
Implementation Method 1
the carbon-containing layer may cause the semiconductor patterns to each have second grains whose average size is less than that of first grains that are included in the cell substrate
Data Source
AI summary
Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.