3D Memory Array Hexagonal Opening Arrangement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3-D memory arrays face limitations in memory cell density and require a significant number of decoder drivers due to the rectangular arrangement of openings, which restricts their efficiency and scalability.
Innovation Solution
The implementation of a staggered, hexagonal arrangement of openings in 3-D memory arrays, where each opening is smaller and enlarged to maintain dielectric thickness while increasing density, and the formation of conductive pillars and storage elements, reduces the number of decoder drivers needed by allowing each memory cell to be uniquely addressed by a pair of conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a rectangular arrangement of openings is used in 3-D memory arrays, then the structure is simple to manufacture, but the memory cell density is limited and the number of decoder drivers required is high
Solution Approach 1:
The patent applies asymmetry by transitioning from a symmetric rectangular arrangement to an asymmetric hexagonal arrangement of openings. This hexagonal pattern allows for more efficient packing of memory cells in three-dimensional space, increasing density while reducing the number of conductive lines required for addressing, thereby reducing decoder driver quantity.
Solution Approach 2:
The patent utilizes three-dimensional stacking of memory cells across multiple floors or levels. By arranging openings in a hexagonal pattern that extends vertically through multiple layers, the design increases memory cell density without proportionally increasing the number of decoder drivers, as cells on different floors can share addressing lines.
2Quantity of substance
If opening size is reduced to increase density, then memory cell density increases, but dielectric thickness is compromised
Solution Approach 1:
The patent compensates for reduced opening dimensions by utilizing the third dimension (vertical stacking). Memory cells are arranged across multiple floors, allowing the overall density to increase through vertical expansion rather than solely through horizontal packing, thus maintaining adequate dielectric thickness while achieving higher density.
Solution Approach 2:
The patent implements a nested structure where multiple memory cells are stacked vertically within a compact footprint. Each floor contains memory cells formed around conductive pillars, with insulation material and additional conductive lines nested between floors, maximizing space utilization while preserving necessary dielectric layers.
Data Source
AI summary
An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.