Solid-State Devices TRIZ Cases

Multiple subpixels share one floating diffusion region, enabling sequential rolling-shutter readout or simultaneous global-shutter capture for higher resolution and dynamic range.

A TiN-capped aluminum conductive pad lowers reflectivity and suppresses hillocks, improving layer alignment, yield, and thermal stability.

Overlapping control and floating gates with insulating layers raises CG-FG coupling ratio, lowering programming voltage and improving erase performance.

Selective cap dielectric etching shapes 3D NAND pillar openings to reduce misalignment, voids, and deck connectivity loss.

A cavity-mounted carrier lets the image sensor move in-plane for anti-shake compensation without increasing mobile camera module height.

A region-specific LED layout and diffuser structure suppress edge bright lines and hot spots while keeping backlight luminance uniform.

AC electromagnetic coupling lights ordered nLED grains through a dielectric layer, avoiding direct bonding and costly alignment transfer.

An extended drain electrode and aligned light blocking layer prevent light leakage from substrate misalignment during LCD bending.

Blind holes filled with a matching light-transmitting planarization layer flatten the camera area and cut diffuse reflection.

A large probe-contact groove paired with smaller conductive-layer grooves prevents probe burn and improves array substrate test signal reliability.

By removing CMP, this FeRAM cell uses a recessed top-electrode layout to cut cost, preserve alignment marks, and improve yield.

A central SPAD electrode with microlens-guided light collection evens the electric field, cuts noise, and improves photon detection.

Concave and convex mesa-edge features improve LED light extraction, current spreading, cutting accuracy, and package reliability.

An etched leadframe isolation region and SOI layout raise die-to-conductor isolation while preserving magnetic sensing for higher-current measurement.

Activated iodine fluorocarbons strengthen hard masks during silicon etching, improving selectivity and vertical high-aspect-ratio patterning.

A recessed layer redirects sub-pixel light to reduce total internal reflection, improving OLED output and limiting crosstalk.

Filling pitted dielectric sidewalls with HDP or SACVD and etching back cuts metal trapping and premature breakdown in high-voltage integrated capacitors.

Varying electrode thickness across same-color OLED sub-pixels offsets size differences, reducing brightness deviation and extending panel life.

Using bonded interconnect metal as a light-blocking layer suppresses hot-carrier emission, dark current, and noise without adding chip thickness.

Shifted auxiliary separation pitches in stacked memory cells raise storage density while preserving electrical isolation and connection reliability.

Pressure and optical sensing are combined to compensate finger contact area changes and improve blood pressure reading accuracy.

A stepped multilayer cap layer smooths flash memory stack sidewalls, protecting the etched layer from leakage and reliability loss.

A UV filter above the photoluminescent layer blocks unabsorbed sub-430 nm light while preserving display color and brightness.

Segmented doping in a display semiconductor layer preserves aperture ratio and charge efficiency while reducing short-circuit risk in high-resolution pixels.

An electromagnetic self-assembly micro-LED structure uses a protruding mesa and passivation layer to raise transfer yield and light extraction.

An inorganic ceramic or crystal package with a bonding layer improves LED heat dissipation, color stability, and lifetime in high-power use.

By overlapping side wiring only on an isolated pad region, this case prevents galvanic corrosion and preserves display electrical connections.

Electrode overlap on partition walls improves rod-type LED light output and durability while a color filter layer cuts external reflection.

A dual-resistance heater drives PCM switching while isolating the RF path outside heating phases to cut off capacitance.

Varying drain sub-region areas keeps gate overlap uniform despite wire misalignment, reducing LCD stitch defects and flicker.

Planar polarization diffraction micro-lenses collimate and deflect micro-OLED light to improve extraction efficiency and reduce crosstalk.

Thermally conductive top and bottom elements spread LED heat across the submount while a molded lens simplifies packaging and supports higher-power use.

An outer edge electrode and shared photoelectric layer keep edge damage from leaking charge into the optical black region, preserving black reference output.

A tailored organometallic emitter increases the energy gap to curb non-radiative decay, boosting OLED quantum yield and lifespan.

Patterned buffer-layer electrodeposition forms copper TFT metal lines without etching, improving display panel yield and lowering cost.

Combining royal-blue and blue pump LEDs with green and red phosphors expands m/p ratio tuning while preserving high color fidelity.

Sidewall spacers and staged etching self-align the MTJ pillar with the SOT-line, reducing current circumvention and improving switching.

Multiple light sources and wavelength conversion keep white, orange, and red output compliant through red vehicle shells of varying thickness.

Electromagnetic alignment uses conductive patterns and staged signals to position and orient light-emitting elements uniformly for display fabrication.

Vertical gate electrodes and a shallow overflow path help maintain saturation signal amount during mechanical shutter operation.

Offset boundaries between stacked LED junction segments reduce dark bands and improve illumination uniformity for camera lighting.

Aromatic nitrile solvents stabilize p-type dopant inks, preventing phase separation and preserving droplet uniformity in printed organic layers.

A stacked SOI diode-transistor cell boosts ionizing radiation sensitivity while reducing chip area by sharing the PN junction and threshold sensing.

Shared signal leads and a flexible compound-eye sensor layout cut wiring complexity and camera thickness while supporting adaptive stereoscopic imaging.

Backside vias connect the device layer to backside metallization to cut series resistance, save die area, and improve IC power and signal delivery.

A vertical-sidewall trench plug cuts thermal budget and lateral diffusion, enabling narrower semiconductor isolation with depth controlled independently.

A three-layer image sensor separates pixels, logic, and memory to enable on-chip neural processing without enlarging the sensor footprint.

Different photodiode areas within a vehicle image sensor improve light collection and image quality without uniformly sacrificing pixel density.

A titanium and TiN annealed ohmic contact forms a spherical-cap silicide that lowers contact resistance and dark current in IC pillars.

A metamaterial reflector redirects transmitted light back to each backside imaging pixel, reducing crosstalk and improving light use.

A 3D flash memory architecture uses cylindrical channel pillars and ferroelectric layers to enable efficient programming, erasing, and reading operations.

Mask insulators enable precise alignment of auxiliary wiring above common electrodes, preventing light blocking and preserving aperture ratio.

Skipping erase verify for inner NAND sub-blocks reduces total erase time while maintaining reliability through outer sub-block verification.

BCl3 gas removes surface metal oxides on source and drain layers, enabling uniform etching rates that resolve performance issues caused by uneven processing.

Buffer contacts allow electrical connections to land without etching through the resistive film, preventing punch-through defects and misalignment issues.

A μOLED architecture uses direct substrate bonding to decouple TFT and OLED layers, enabling ultra-high pixel density.

Varying microcavity optical path lengths select colors during one transfer, eliminating multi-step alignment errors.

A piezo-effect transistor device uses pressure to modulate resistance, enabling scalable switching with transverse current flow.

Antiparallel ferromagnetic films in the anchoring layer stabilize magnetization states for reliable magnetic storage operation.

A low compressive TiNx layer maintains electrical conductivity while preventing structural curvature in microelectromechanical devices.

Removing the charge trapping layer adjacent to top select gate electrodes eliminates threshold voltage shifts that degrade device reliability.

An organic thin film transistor uses an adhesive layer with patterned hydrophilic and hydrophobic regions to guide metal nanoparticle placement.

Photocurable monomer composition with high cross-linking density forms a hard organic layer for OLED encapsulation.

A multiple light emitter device combines violet and blue light sources to produce a high-quality disinfecting white light spectrum.

An oxide intermediate layer bonds the organic insulating layer to the second conductive layer, maintaining direct electrical contact.

Combining anode and pad cover electrode formation into a single mask process reduces manufacturing costs while maintaining precision.

Patterned inorganic insulation encloses electrode areas to enable uniform organic layer deposition, eliminating costly shadow mask alignment steps.

Odd and even layer bit line selection switch elements apply distinct current limiting methods to stabilize resistance change operations across all array planes.

A vertical semiconductor device uses dual data storage structures to store multiple bits in a single memory cell.

Segmented pixels with insulating layers reduce optical and electrical crosstalk, enabling high radiating area efficiency while maintaining reliable operation.

A micro LED structure uses a tilted side surface with a reflective layer to redirect side light toward the top surface.

Opposite conductivity doping in seed islands enables electron tunneling, resolving insulating barriers that hinder current flow in optoelectronic devices.

XeF2 vapor-phase etching creates precise airgaps in silicon substrates, eliminating stiction risks during the release of wide bandgap microstructures.

A quantum dot array substrate integrates a protective filter layer to block ultraviolet and blue light while transmitting red and green wavelengths.

Segmented external connection terminals and an electromagnetic shield structure resolve EMI susceptibility while supporting multiple memory card standards.

A sidewall insulating layer protects memory hole walls from etching, preventing sidewall damage and maintaining cell integrity.

Self-assembled monolayers coat masks to repel deposition materials, preventing shadow defects and irregular patterns on substrates.

A dry etching method removes stable metals like ruthenium and tantalum using fluorine-containing interhalogen compounds at low temperatures.

Removing stress liners from the trench isolation region enables void-free dielectric formation, preventing electrical shorts and enhancing reliability.

A grounded conductive electrode in the wiring region of a thin film transistor array substrate discharges high-voltage static electricity.

Non-adhesive die alignment members prevent adhesive residue and fluid migration, ensuring high-quality sintered joints without cleaning steps.

Monolithic metasurface lens integration on wafer substrates eliminates bulky multi-lens assemblies and reduces manufacturing complexity.

A touch sensor design merges connection patterns with contact electrodes to reduce manufacturing complexity.

Slit structures separate vertical channel pillars in a 3D memory device, increasing storage capacity without deteriorating operation performance.

Segmented upper connection structures distribute capacitive load across spaced points to enhance operation speed in semiconductor memory devices.

Coil structures generate magnetic fields to precisely position micro LED pins, resolving low yield ratios in mass transfer processes.

A thermocompression bonder measures lateral force during contact to apply corrective alignment motions.

A Talbot imaging system uses a phase gradient device to scan focal spots over an object for high resolution.

A graphene vertical semiconductor channel replaces silicon in three-dimensional memory stacks to boost electron mobility.

An assist layer with negative magnetic anisotropy generates initial torque to reduce electrical current requirements for magnetization switching.

Sampling unit synchronizes detection with galvano-scanner peak positions to eliminate image distortion from non-linear scanning velocity.

Epitaxial sensor arrays bonded to flexible membranes enable conformal wrapping onto curved surfaces without adhesives.

An embedded diode array with doped semiconductor regions connects to phase change elements to minimize voltage drop across the memory structure.

Replacing expensive ceramic housings, this composite material reduces manufacturing costs while maintaining UV resistance through wide energy gap fillers.

Grooved surface processing layers prevent hole transport solution spreading to adjacent pixels, eliminating color mixing in organic light-emitting displays.

Bending the flexible substrate positions the sensing circuit closer to the panel, reducing module area while maintaining touch accuracy.

Inorganic buffer absorbs plasma damage from high-speed sputtering, preventing color shifts and efficiency loss in OLED cathodes.

Single-step lamination of a multilayer PWB with integral RF cages reduces fabrication complexity while maintaining high RF performance.

A silicon photomultiplier integrates nonlinear elements in microcells to separate timing and energy signals.

An encapsulation structure uses an aluminum carbon layer to bond inorganic and organic films.