TFT Array Panel Electrode Layout for Stable Parasitic Capacitance
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Solution Overview
Problem
The existing manufacturing processes for liquid crystal display (LCD) thin film transistor array panels face issues with parasitic capacitance due to misalignment of gate and data wires, leading to display quality deterioration such as stitch defects and flicker.
Innovation Solution
The thin film transistor array panel design includes a drain electrode with sub-regions of varying planar areas and a dummy drain electrode with corresponding sub-regions, ensuring a uniform overlapping area with the gate electrode, thereby maintaining consistent parasitic capacitance despite alignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used for LCD thin film transistor array panels, then production efficiency is maintained, but parasitic capacitance varies due to misalignment of gate and data wires, leading to display quality deterioration
Solution Approach 1:
The patent changes the geometric parameters of the drain electrode by dividing it into multiple sub-regions with different planar areas. This parameter modification allows the overlapping area with the gate electrode to remain uniform even when misalignment occurs, thereby stabilizing parasitic capacitance and improving display quality reliability without requiring higher manufacturing precision
Solution Approach 2:
The drain electrode is segmented into multiple sub-regions (first sub-region, second sub-region, third sub-region, etc.) with progressively different planar areas. This segmentation strategy enables the overall overlapping area to remain constant despite misalignment, as the varying areas of sub-regions compensate for positional deviations, thus resolving the contradiction between manufacturing precision and display quality stability
2Reliability
If the overlapping area between gate electrode and drain electrode is increased to reduce parasitic capacitance variation, then display quality improves, but the area occupied by the drain electrode increases, reducing the opening ratio of the display panel
Solution Approach 1:
The patent modifies the area distribution parameter of the drain electrode by creating sub-regions with different planar areas that are strategically positioned. This allows the total area of the drain electrode to be minimized while maintaining a uniform overlapping area with the gate electrode, thus improving display quality consistency without sacrificing opening ratio
Solution Approach 2:
Different sub-regions of the drain electrode are assigned different planar areas based on their local positioning requirements. This local quality differentiation enables the overlapping area to remain uniform across the entire gate electrode length while keeping the total drain electrode area minimal, resolving the contradiction between display quality consistency and area occupation
Data Source
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AI summary
A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.