Non-volatile Memory Erase Verify Skip for NAND Sub-blocks
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Solution Overview
Problem
Erase speed variations in non-volatile memory cells lead to performance issues due to the need for multiple erase verify operations and dynamic voltage changes, which complicate the design and require additional resources.
Innovation Solution
The proposed solution involves skipping erase verify operations for certain memory cells based on a predetermined system parameter, applying erase voltage pulses to both outer and inner sub-blocks, and performing erase verify only after the outer sub-blocks successfully erase, thereby optimizing the erase process and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple erase verify operations are performed to ensure complete erasure of all memory cells, then erasure reliability is improved, but erase time and process complexity increase
Solution Approach 1:
The memory block is divided into outer sub-blocks and inner sub-blocks. Different erase verify strategies are applied to each segment: outer sub-blocks undergo multiple erase verify operations to ensure complete erasure, while inner sub-blocks use fewer verify operations since they are erased later anyway. This segmentation allows the system to maintain high erasure reliability for critical areas while reducing overall erase time.
Solution Approach 2:
The erase operation applies erase voltage pulses in a specific sequence: first to outer sub-blocks, then to inner sub-blocks. By performing the erase operation on outer sub-blocks first and verifying their erasure, the system establishes a baseline of complete erasure before proceeding to inner sub-blocks. This preliminary action on outer sub-blocks allows subsequent inner sub-block erasure to be verified with fewer operations.
2Manufacturing precision
If dynamic voltage changes are implemented during erase operations to compensate for erase speed variations, then erasure uniformity is improved, but device complexity and resource requirements increase
Solution Approach 1:
The erase operation is segmented into distinct phases targeting outer sub-blocks first, then inner sub-blocks. Each segment receives appropriate erase voltage pulses without requiring complex dynamic voltage adjustment circuits. The segmentation itself provides the uniformity needed, as each segment's erase characteristics are accounted for by the sequential processing approach rather than complex real-time voltage control.
Solution Approach 2:
The system changes the timing and sequencing parameters of erase voltage pulse application rather than dynamically adjusting voltage magnitude. By controlling when each sub-block receives erase pulses (outer first, then inner), the system achieves uniform erasure across all cells without requiring complex voltage regulation circuitry. This parameter-based control simplifies the device architecture while maintaining erasure uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for the erase process and simplifies the design by minimizing the need for dynamic operations and additional state information storage, while ensuring efficient erasure of non-volatile memory cells.
Implementation Method 1
An erase operation can include a number of erase cycles, where each cycle comprises an erase portion follow by a erase verify portion. In one embodiment of the erase portion, voltages are applied to a block of non-volatile memory cells to provide a positive channel-to-gate voltage for the memory cells of the block to drive electrons out of the charge-storing material of the memory cells, thereby reducing the threshold voltage of the memory cells.
Implementation Method 2
In the verify portion, an erase verify voltage is applied to the control gates of the memory cells via the word lines of the block, and sensing circuitry is used to sense currents to determine if the memory cells have been sufficiently erased. Memory cells with threshold voltages below the erase verify level will turn on in response to the erase verify voltage being applied to the control gates of the memory cells via the word lines of the block.
Data Source
AI summary
A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks of the block. Erase verify is performed between erase voltage pulses for NAND strings in the outer sub-blocks while skipping erase verify for NAND strings in the inner sub-blocks. Performing erase verify between erase voltage pulses for NAND strings in the inner sub-blocks is started at a predetermined number of erase voltage pulses after the NAND strings in the outer sub-blocks successfully erase verify.