Semiconductor Memory Device Upper Connection Structures
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices is compromised due to various factors, necessitating improvements in their design to enhance integration and stability.
Innovation Solution
A semiconductor memory device is designed with a memory cell array on a substrate, featuring a bit line connected to the memory cell array, a peripheral circuit with a transistor, a conductive line between the memory cell array and the transistor, and upper and lower connection structures that connect the bit line and conductive line, respectively, to improve operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional semiconductor memory device is designed to improve degree of integration, then storage capacity increases, but operational reliability deteriorates due to various causes
Solution Approach 1:
The connection between bit line and conductive line is divided into multiple upper connection structures instead of a single structure. This segmentation reduces the loading effect on the bit line by distributing the capacitive load across multiple smaller connection points, thereby improving operational reliability while maintaining the three-dimensional integrated structure
Solution Approach 2:
Multiple upper connection structures serve as intermediaries between the bit line and the conductive line. These intermediate connection points reduce the direct capacitive coupling between the bit line and conductive line, minimizing the loading effect and threshold voltage degradation while preserving the high-density three-dimensional architecture
2Device complexity
If conventional connection structures are used between bit line and transistor, then device complexity is reduced, but loading effect on bit line increases and operation speed deteriorates
Solution Approach 1:
The single connection structure is segmented into multiple upper connection structures spaced apart from each other. This segmentation reduces the total capacitive load on the bit line by distributing the connection points, thereby improving operation speed without significantly increasing device complexity
Solution Approach 2:
The connection structures are arranged in a spatial distribution pattern rather than a simple linear arrangement. By utilizing the three-dimensional space efficiently and spacing the upper connection structures apart, the design reduces parasitic effects and improves signal transmission speed while maintaining manageable device complexity
3Ease of manufacture
If conventional connection structures are used between bit line and transistor, then manufacturing is simplified, but threshold voltage distribution degrades
Solution Approach 1:
The connection path is segmented into multiple upper connection structures that are spaced apart, reducing the capacitive coupling between bit line and conductive line. This segmentation minimizes the loading effect that causes threshold voltage degradation, while the structures can be manufactured using standard semiconductor fabrication processes
Solution Approach 2:
The design changes the spatial parameters of the connection structures by spacing multiple upper connection structures apart from each other. This parameter change reduces the effective capacitive load and minimizes threshold voltage degradation, while remaining compatible with existing manufacturing capabilities
Data Source
AI summary
A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array disposed on a substrate, a bit line connected to the memory cell array, a peripheral circuit disposed between the memory cell array and the substrate, the peripheral circuit including a transistor, a conductive line disposed between the memory cell array and the transistor, a lower connection structure connecting the conductive line and the transistor, and two or more upper connection structures connecting the bit line and the conductive line, the two or more upper connection structures being spaced apart from each other.