3D Gate-Coupled Memory Cells for High CG-FG Coupling Ratio

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Solution Overview

Problem

Manufacturing memory cells with a high control gate (CG)-to-floating gate (FG) gate coupling ratio (GCR) is challenging due to the risk of damaging underlying semiconductor material, which affects the programming voltage and erase performance of split gate memory cells.

Innovation Solution

A memory cell design featuring a substrate with doped regions, a floating gate overlapping the channel and doped regions, a control gate with a wider second portion overlapping the floating gate, and insulation members to optimize the CG-FG GCR, including polysilicon materials and specific insulation layer configurations to enhance the coupling ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the control gate is positioned to maximize overlap with the floating gate for high CG-FG GCR, then programming voltage efficiency and erase performance are improved, but the underlying semiconductor material may be damaged during manufacturing

Engineering Contradiction:

Improveerase performanceVSAvoiddamage to semiconductor material

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An insulation layer is introduced as an intermediary between the control gate and the semiconductor substrate. This insulation layer allows the control gate to be positioned directly over the floating gate for maximum coupling while preventing direct contact between the control gate and the substrate, thereby avoiding damage to the semiconductor material during manufacturing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The control gate structure is replicated in multiple portions (first portion and second portion) positioned at different locations. The second portion is positioned to overlap with the floating gate for maximum coupling, while the first portion serves as a backup or alternative coupling path, ensuring reliable operation without requiring excessive positioning precision that could damage the substrate.

Inventive Principle:

Principle #26Copying

2Use of energy by moving object

If the control gate is positioned to maximize overlap with the floating gate for high CG-FG GCR, then programming voltage requirements are reduced, but manufacturing precision requirements increase due to the risk of material damage

Engineering Contradiction:

Improveprogramming voltageVSAvoidgate positioning precision

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The control gate is segmented into multiple portions positioned at different locations relative to the floating gate. This segmentation allows the second portion to provide maximum overlap for low programming voltage while the first portion provides a safety margin, reducing the overall manufacturing precision requirement compared to a single precise positioning approach.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The insulation layer thickness and material properties are optimized to allow the control gate to be positioned at specific heights and locations. By adjusting these parameters, the system achieves maximum CG-FG coupling for low programming voltage while the insulation layer provides a buffer that reduces the sensitivity to positioning variations.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If the control gate is positioned to maximize overlap with the floating gate for high CG-FG GCR, then erase performance is improved, but device complexity increases due to the need for multiple insulation members

Engineering Contradiction:

Improveerase performanceVSAvoidinsulation member structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The insulation layer serves multiple functions simultaneously: it isolates the control gate from the substrate to prevent damage, provides a platform for positioning the control gate over the floating gate for maximum coupling, and acts as part of the overall device architecture that enables high CG-FG GCR. This multi-functionality reduces the need for separate structural elements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230345718A1Memory cells with three-dimensional gate coupling and methods of forming thereof

Publication Date: 2023.10.26 GLOBALFOUNDRIES SINGAPORE PTE LTD

AI summary

A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.