FeRAM Cell Top Electrode Recess Layout Without CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and yield reduction issues associated with using chemical mechanical planarization (CMP) processes in forming ferroelectric random-access memory (FeRAM) devices, which can lead to obscured alignment marks and decreased reliability due to slurry residue accumulation.
Innovation Solution
A method of forming FeRAM devices without using a CMP process to define the bottom electrode, resulting in a bottom electrode that conforms to the underlying structure with interior recesses, allowing the ferroelectric and top electrodes to be disposed within these recesses, thereby reducing costs and improving photolithography process windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical planarization (CMP) process is used to form bottom electrode, then planar surface is achieved, but manufacturing cost increases and reliability decreases due to slurry residue accumulation
Solution Approach 1:
The patent removes the CMP process step from the fabrication sequence, extracting the problematic slurry residue accumulation issue from the manufacturing flow. The bottom electrode is formed directly on the lower insulating structure without CMP planarization, eliminating the source of reliability problems while still achieving functional devices.
Solution Approach 2:
Instead of planarizing the surface to achieve a flat top, the invention inverts the approach by accepting the non-planar surface created by CMP (when used for other purposes) or by direct formation, and designing the subsequent ferroelectric layer and top electrode to conform to this non-planar surface. This inversion eliminates the need for CMP while maintaining device functionality.
2Manufacturing precision
If chemical mechanical planarization (CMP) process is used to form bottom electrode, then planar surface is achieved, but manufacturing cost increases
Solution Approach 1:
The CMP process step is extracted and removed from the fabrication sequence. The bottom electrode is formed directly on the lower insulating structure without subsequent CMP planarization, eliminating the associated material costs, equipment usage costs, and processing time costs while still achieving functional devices.
3Manufacturing precision
If CMP process is used to define bottom electrode, then alignment marks are obscured, but this is an acceptable trade-off for achieving planar surface
Solution Approach 1:
The CMP process is removed from the fabrication sequence, which eliminates the step that causes alignment mark obscuration. By forming the bottom electrode directly without CMP, the alignment marks remain visible throughout the subsequent fabrication processes, preventing information loss.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The top electrode has interior surfaces defining a recess within an upper surface of the top electrode. A masking layer contacts a bottom of the recess and extends to over the upper surface of the top electrode. An interconnect extends through the masking layer and to the top electrode. The interconnect is directly over the upper surface of the top electrode.