Piezo-Effect Transistor Device for Scalable Logic Applications
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Solution Overview
Problem
Conventional CMOS FETs face scalability issues due to short channel effects, few-dopant fluctuation, and high impedance, limiting clock speeds and requiring large-area devices in power-hungry applications, while building multilayer structures is complex due to the need for single crystal silicon.
Innovation Solution
A piezo-effect transistor (PET) device is introduced, comprising a piezoelectric material between electrodes and a piezoresistive material, where the electrical resistance of the piezoresistive material is controlled by applied voltage-induced pressure, enabling scalable and efficient switching with transverse current flow, thus bypassing the limitations of FET geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional FET geometry is used, then electrostatic control is achieved, but impedance is high and area is large
Solution Approach 1:
The patent transitions from planar FET geometry to a vertical tunnel FET structure where current flows in the vertical dimension through a thin channel. This dimensional change reduces the device footprint area while maintaining control, as the gate electrode can control carrier flow through the vertical tunneling path without requiring large lateral dimensions.
Solution Approach 2:
The patent employs thin film structures for the channel and gate oxide layers, enabling the vertical tunnel FET configuration. The thin channel film allows quantum mechanical tunneling while the thin gate oxide provides effective electrostatic control, together achieving low impedance with reduced device area compared to conventional FETs.
2Productivity
If device scaling is pursued, then integration density increases, but short channel effects and dopant fluctuation worsen
Solution Approach 1:
The patent replaces the conventional drift-diffusion transport mechanism with quantum mechanical tunneling as the primary carrier transport mechanism. This substitution eliminates the need for dopant gradients and traditional channel control, thereby avoiding short channel effects and dopant fluctuation even as devices scale to higher integration densities.
Solution Approach 2:
The patent changes the fundamental transport parameter from drift-diffusion to tunneling by adjusting the channel thickness to the nanometer scale. This parameter change enables effective mass transport through the thin channel without requiring high dopant concentrations, thus maintaining device performance stability during scaling.
3Length of moving object
If FET channel length is reduced for scaling, then device size decreases, but speed decreases proportionally to 1/L²
Solution Approach 1:
The patent replaces velocity-dependent drift transport with field-dependent tunneling transport. In the tunneling mechanism, carrier velocity is not directly proportional to the electric field, breaking the 1/L² speed limitation. This allows further channel length reduction without proportional speed degradation, enabling continued scaling.
4Adaptability or versatility
If multilayer structures are built in CMOS, then functionality increases, but manufacturing complexity increases significantly
Solution Approach 1:
The patent segments the device into distinct vertical layers (gate electrode, gate oxide, thin channel, source/drain contacts) that can be formed using sequential deposition and patterning steps. This segmentation allows each layer to be optimized independently while maintaining compatibility with standard CMOS manufacturing processes, increasing functionality without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PET device achieves low ON impedance, eliminates short-channel effects, and allows for multilayer structures, enhancing carrier transport and reducing power consumption, making it suitable for high-capacity memories and logic applications.
Implementation Method 1
a piezoelectric (PE) material disposed between first and second electrodes... such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material
Implementation Method 2
a piezoresistive (PR) material disposed between the second electrode and a third electrode... such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material
Data Source
AI summary
A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material.