Doped Semiconductor Layer Layout for High-Resolution Display Pixels
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Solution Overview
Problem
Increased resolution in electronic devices leads to reduced semiconductor layer widths, causing performance issues and potential short circuits due to design flaws in contact holes during manufacturing.
Innovation Solution
Incorporating a semiconductor layer with IIIA and VA group elements, specifically with doping concentrations greater than 0 and less than or equal to 10^16 atoms/cm3, to improve the design and reduce defects such as insufficient aperture ratio and short circuits by optimizing the semiconductor layer's configuration and doping regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the electronic device is increased, then the display quality is improved, but the manufacturing space of semiconductor layers is reduced causing width variation and performance degradation
Solution Approach 1:
The semiconductor layer is segmented into three distinct portions: a first portion connected to the data line, a second portion connected to the drain, and a third portion connecting between them. This segmentation allows each portion to be optimized independently for its specific function while maintaining overall performance in high-resolution devices.
Solution Approach 2:
Different portions of the semiconductor layer are assigned different doping concentrations to optimize local properties. The first and second portions have doping concentrations greater than 10^16 atoms/cm³ for good electrical contact, while the third portion has doping concentration between 10^14-10^16 atoms/cm³ to balance electrical performance and structural stability in the constrained space.
2Productivity
If the distance between elements is reduced to increase resolution, then the device density is improved, but conductive layers are exposed during manufacturing causing short circuits
Solution Approach 1:
The semiconductor layer is designed to extend beyond the gate electrode boundaries in the third portion, creating a preliminary protective structure that prevents exposure of conductive layers during contact hole formation. This design anticipates and prevents the short circuit problem before it occurs during manufacturing.
Solution Approach 2:
The semiconductor layer is formed to overlap with the gate electrode and extend beyond its boundaries before the contact hole formation process. This preliminary positioning ensures that when contact holes are etched, the conductive layers remain covered, preventing short circuits between adjacent elements.
3Area of stationary object
If the semiconductor layer width is reduced to increase aperture ratio, then the light transmission is improved, but the manufacturing precision control becomes difficult causing performance variation
Solution Approach 1:
The doping concentration parameter is changed across different portions of the semiconductor layer to achieve the desired width and shape. By controlling doping concentration (10^14-10^16 atoms/cm³ in the third portion), the layer maintains structural integrity and predictable formation behavior, improving manufacturing precision control while achieving high aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the aperture ratio and light-emitting area/display area ratio while maintaining charge efficiency, reducing the risk of short circuits and improving manufacturing feasibility, especially in high-resolution products.
Implementation Method 1
At least one portion of the third portion includes at least one of IIIA group element and VA group element, and the doping concentration of the at least one of IIIA group element and VA group element is greater than 0 and less than or equal to 10{circumflex over (16)} (1016) atoms/cm3
Data Source
AI summary
An electronic device includes a substrate, a data line disposed on the substrate, a drain disposed on the substrate and a semiconductor layer disposed on the substrate. The semiconductor layer includes a first portion connected to the data line, a second portion connected to the drain, and a third portion connected between the first portion and the second portion. At least one portion of the third portion includes at least one of IIIA group element and VA group element, and the doping concentration of the at least one of IIIA group element and VA group element is greater than 0 and less than or equal to 10{circumflex over ( )}16 atoms/cm3.