Backside Via IC Structures for Lower-Resistance Signal Routing
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Solution Overview
Problem
Conventional integrated circuit (IC) components face challenges in efficiently passing signals and power due to large series resistance and increased die area and cost associated with through-silicon vias (TSVs), which are inadequate for modern complex electronics, especially in 3D ICs and silicon-on-insulator technologies.
Innovation Solution
The integration of backside vias that couple the device layer directly to backside metallization, reducing routing distance and resistance, and allowing thicker, lower-resistance metallization layers, thereby reducing the need for upper-level metals and freeing up resources for on-die circuit routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to pass signals and power, then electrical coupling between devices and external components is achieved, but large series resistance and increased die area and cost occur
Solution Approach 1:
The patent inverts the conventional approach by placing vias on the backside of the substrate rather than through the entire thickness from the front. This backside via configuration reduces the via length and associated resistance while minimizing the die area required, as the vias do not need to traverse the full substrate thickness.
Solution Approach 2:
The patent transitions from a conventional front-side via configuration to a backside via configuration, effectively utilizing the third dimension (substrate thickness) in a different orientation. This dimensional repositioning allows for shorter via lengths and reduced series resistance while maintaining electrical coupling functionality.
2Reliability
If through-silicon vias (TSVs) are used to pass signals and power, then electrical coupling between devices and external components is achieved, but large series resistance occurs
Solution Approach 1:
The patent inverts the conventional approach by placing vias on the backside of the substrate rather than through the entire thickness from the front. This backside via configuration reduces the via length and associated resistance while minimizing the die area required, as the vias do not need to traverse the full substrate thickness.
Solution Approach 2:
The patent changes the via configuration parameter from front-side to back-side, which directly reduces the via length and series resistance. This parameter change optimizes the electrical coupling efficiency by minimizing the resistive path while maintaining the necessary electrical connections.
3Ease of manufacture
If conventional single-sided IC components are used, then manufacturing is simpler, but routing efficiency and signal delivery are limited
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional dimension for via placement, enabling more efficient routing and signal delivery. This three-dimensional via configuration improves signal delivery efficiency while maintaining manufacturing feasibility through established backside processing techniques.
Data Source
AI summary
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.