Solid-state imaging device, manufacturing method thereof, and electronic apparatus
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Solution Overview
Problem
The existing solid-state imaging devices face challenges with light emission due to hot carriers from MOS transistors, leading to dark current and random noise, which increases the thickness of the semiconductor chip and complicates manufacturing, thereby reducing yield and increasing costs.
Innovation Solution
A solid-state imaging device is configured by bonding semiconductor chip sections with a light blocking layer formed from an electrically-conductive film of the same layer as the connecting interconnects, positioned between the pixel array and logic circuit sections, to prevent light emission and reduce chip thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a light blocking layer is formed separately from the interconnect layer to prevent hot carrier light emission, then dark current and random noise are reduced, but the chip thickness increases and manufacturing complexity increases
Solution Approach 1:
The interconnect layer is designed to serve dual functions: electrical connection and light blocking. By forming the light blocking layer from the same electrically-conductive film as the connecting interconnects, the patent eliminates the need for a separate light blocking layer, thus reducing chip thickness and manufacturing complexity while still preventing hot carrier light emission that causes dark current and random noise
Solution Approach 2:
The patent merges the light blocking function with the interconnect function by using the same conductive film for both purposes. This combination reduces the number of separate layers and simplifies the manufacturing process, directly addressing the contradiction between reducing harmful effects and maintaining device simplicity
2Object-affected harmful factors
If the light blocking layer is formed from a separate layer, then light emission from hot carriers is blocked, but the manufacturing process becomes more complex and yield decreases
Solution Approach 1:
The interconnect layer performs both electrical connection and light blocking functions simultaneously. By using the same conductive film for both purposes, the patent reduces manufacturing steps and complexity, thereby improving manufacturing yield while still effectively blocking light emission from hot carriers that would otherwise cause dark current and random noise
3Device complexity
If chip thickness is reduced by integrating the light blocking function into the interconnect layer, then manufacturing is simplified, but the ability to block light emission must be maintained
Solution Approach 1:
The conductive film forming the interconnect layer is designed to simultaneously provide electrical connection and light blocking capabilities. This multi-functional design simplifies manufacturing by eliminating separate light blocking layers while maintaining the ability to block light emission from hot carriers, thus resolving the contradiction between manufacturing simplicity and light blocking effectiveness
Solution Approach 2:
The patent utilizes the inherent optical properties of the conductive film material to block light emission. By selecting appropriate conductive materials and optimizing their thickness, the interconnect layer achieves sufficient light blocking capability while maintaining its electrical function, thereby simplifying manufacturing without compromising light emission blocking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses light emission from hot carriers, reducing dark current and random noise, while minimizing chip thickness and simplifying the manufacturing process, thereby improving yield and reducing costs.
Implementation Method 1
a light blocking layer formed from an electrically-conductive film of the same layer as a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections
Data Source
AI summary
Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.