Stacked Image Sensor Layout for On-Chip Neural Processing

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Solution Overview

Problem

Current image sensor technologies face limitations in executing advanced processing within a chip, particularly for diversification and acceleration of image processing, as well as protecting personal information.

Innovation Solution

A stacked light receiving sensor is proposed, comprising multiple substrates with a pixel array section, analog and logic circuits, a memory storing a neural network computing model, and a processing section that executes processing based on this model, allowing for advanced processing within the chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a single-chip image sensor with stacked structure is used for miniaturization, then the device size is reduced, but the capability to execute advanced processing within the chip is limited

Engineering Contradiction:
Improvedevice sizeVSAvoidprocessing capability
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The image sensor is divided into multiple functional substrates stacked together: a first substrate containing pixel arrays, a second substrate containing logic circuits and neural network processing sections, and a third substrate containing memory. This segmentation allows each layer to be optimized for its specific function while collectively enabling advanced processing capabilities within a compact stacked structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar single-chip structure to a three-dimensional stacked structure by arranging different functional components on separate substrates stacked in the vertical dimension. This dimensional change enables increased processing capability and functionality without proportionally increasing the device footprint area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple substrates are stacked to enhance processing capability, then advanced processing within chip is enabled, but device complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The second substrate is designed to perform multiple functions: it contains logic circuits for general signal processing, neural network processing sections for AI-based image processing, and memory for data storage. This multi-functionality reduces the need for separate dedicated substrates for each function, thereby managing complexity while enhancing processing capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple functional components (logic circuits, neural network processing sections, and memory) are merged onto the second substrate, creating a multifunctional intermediate layer that connects the pixel arrays on the first substrate with additional processing capabilities without requiring separate substrates for each function.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11792551B2Stacked light receiving sensor and electronic apparatus
Publication Date: 2023.10.17 SONY SEMICON SOLUTIONS CORP
  • US11792551B2 patent drawing
  • US11792551B2 patent drawing
  • US11792551B2 patent drawing

AI summary

A stacked light receiving sensor according to one embodiment includes a first substrate in a first layer, a second substrate joined with the first substrate and formed in a second layer, and a third substrate joined with the second substrate and formed in a third layer. An analog circuit reads a pixel signal from a pixel array. A logic circuit is connected to the analog circuit and outputs the pixel signal. A processing section executes processing based on a neural network computing model, on data based on the pixel signal. The pixel array is disposed on the first layer. The analog circuit is disposed on any one or more of the first to third layers. The logic circuit, the processing section, and a memory are disposed on any one or more of the second and third layers.