3D Flash Memory Architecture with FeFET Cylindrical Pillars
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Solution Overview
Problem
Current 3D AND flash memory technologies face challenges in achieving smaller size, higher efficiency, and faster operation to support increasing memory capacities in smaller electronic devices while maintaining battery life and performance.
Innovation Solution
The development of a 3D flash memory architecture that incorporates cylindrical channel pillars and ferroelectric materials to form Ferroelectric Field Effect Transistors (FeFETs), with a gate stack structure including insulating and conductive pillars, and a ferroelectric layer, allowing for efficient programming, erasing, and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D flash memory architecture is used, then device size is larger, but memory capacity per area is lower
Solution Approach 1:
The patent implements a nested structure where conductive pillars are positioned within cylindrical channel pillars, and multiple gate layers wrap around these cylindrical structures. This nesting arrangement maximizes space utilization and enables higher memory capacity density within a reduced footprint area.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to three-dimensional cylindrical structures with vertical channel pillars and wrapped gate layers. This dimensional change enables significantly higher storage density by utilizing the third dimension (vertical stacking) rather than expanding horizontally.
2Speed
If conventional flash memory architecture is used, then operation speed is slower, but reading/writing operations take longer time
Solution Approach 1:
The patent divides the memory structure into multiple independently addressable gate layers wrapped around cylindrical channel pillars. This segmentation allows parallel access to different memory cells through different gate layers, enabling faster read and write operations by reducing the time required to access and manipulate data.
Solution Approach 2:
The patent utilizes ferroelectric materials with switchable polarization states to enable rapid data writing. The ferroelectric effect allows for fast switching between logic states (0 and 1) by applying electric fields, significantly reducing write operation time compared to conventional charge-trapping mechanisms.
3Area of stationary object
If device size is reduced to increase memory capacity, then area efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The cylindrical channel pillar structure serves multiple functions simultaneously: it acts as the charge storage region, the structural framework for wrapping gate layers, and the spatial organizer for positioning conductive pillars. This multi-functionality reduces the need for separate components and simplifies the overall manufacturing process despite the three-dimensional architecture.
4Productivity
If ferroelectric materials are used to form FeFETs, then programming speed improves, but energy consumption may increase
Solution Approach 1:
The patent employs periodic pulsed voltage applications to the ferroelectric layer to achieve desired polarization states. By using short, high-amplitude voltage pulses rather than continuous voltage application, the system achieves fast programming while minimizing energy consumption, as the ferroelectric material retains its state without continuous power input.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a 35% reduction in area, allowing for more memory in smaller spaces, faster read speeds of approximately 100 ns, program speeds of 1 μs, and erase speeds of 1 μs, while maintaining efficient battery operation.
Implementation Method 1
a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar
Data Source
AI summary
A 3D flash memory is provided to includes a gate stack structure comprising a plurality of gate layers electrically insulated from each other, a cylindrical channel pillar vertically extending through each gate layer of the gate stack structure, a first conductive pillar vertically extending through the gate stack structure, the first conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, and a second conductive pillar extending through the gate stack structure, the second conductive pillar being located within the cylindrical channel pillar and being electrically connected to the cylindrical channel pillar, the first conductive pillar and the second conductive pillar being separated from each other. The 3D flash memory also includes a ferroelectric layer disposed between gate layers of the gate stack structure and the cylindrical channel pillar.