Cross Point Memory Device Layer Current Steering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multilayer cross point variable resistance nonvolatile memory devices face challenges in achieving stable resistance change operations across all layers due to differences in resistance change characteristics between odd and even layers, making uniform current limiting methods ineffective.
Innovation Solution
A nonvolatile memory device with a multilayer cross point structure incorporating a variable resistance element and a current steering element connected in series, along with a hierarchical bit line structure and PMOS and NMOS transistors for bit line selection switch elements, ensures stable resistance value setting in all layers by controlling current direction and magnitude.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a uniform current limiting method is used across all layers, then the device complexity is reduced and ease of manufacture is improved, but the reliability of resistance change operation deteriorates due to differences in characteristics between odd and even layers
Solution Approach 1:
The patent applies different current limiting methods to different layers: odd layers use one current limiting approach while even layers use another. This local differentiation allows each layer type to operate with its optimized characteristics, resolving the reliability issue while maintaining manageable device complexity through a systematic rather than fully customized approach.
Solution Approach 2:
The memory device is segmented into odd and even layers, each with dedicated current limiting circuits tailored to their specific characteristics. This segmentation allows independent optimization of current limiting for each layer type, ensuring reliable resistance change operations across all layers without requiring a complex unified solution.
2Reliability
If different current limiting methods are used for odd and even layers, then the reliability of resistance change operation is improved, but the device complexity increases
Solution Approach 1:
The patent implements local quality by assigning specific current limiting methods to specific layer types (odd vs even). Each layer type has its own optimized current limiting circuit, which improves reliability by matching the circuit characteristics to the layer's specific resistance change behavior, while the overall complexity remains controlled through this systematic differentiation.
3Ease of manufacture
If the variable resistance element structure is standardized across all layers, then the ease of manufacture is improved, but the stability of resistance change characteristics deteriorates due to layer-dependent variations
Solution Approach 1:
The patent maintains standardized variable resistance element structures across all layers for ease of manufacture, while compensating for layer-dependent variations through layer-specific current limiting methods. This approach preserves manufacturing simplicity while achieving stable resistance change characteristics by adapting the electrical characteristics to each layer's specific behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable writing operations across all layers, facilitating fast and reliable memory operations suitable for mass memory applications by ensuring consistent low and high resistance state settings regardless of the memory cell's layer.
Implementation Method 1
a variable resistance element (10) that changes between a high resistance state and a low resistance state according to a polarity of an applied voltage
Implementation Method 2
a current steering element (29) connected in series with the variable resistance element (10) and having nonlinear current-voltage characteristics
Data Source
AI summary
Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively. Each of the even and odd layer bit line selection switch elements has both a bit line selection function and a current limiting function in low resistance writing.