Integrated Capacitor Sidewall Smoothing to Prevent Breakdown
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Solution Overview
Problem
The challenge in forming integrated high voltage capacitors is the parasitic breakdown caused by trapped metal particles in the rough sloped dielectric sidewall portion, which is difficult to address in existing methods, especially for extra-high voltage applications above 5,000 volts, where increased capacitance is needed to reduce semiconductor area and prevent premature breakdown.
Innovation Solution
The solution involves using high density plasma (HDP) or sub-atmospheric chemical vapor deposition (SACVD) to fill the pores in the sloped sidewall portion, followed by a blanket etch to reduce roughness and prevent metal trapping, allowing for the formation of a discontinuous dielectric layer that maintains the original slope angle without introducing new materials or processes, thereby reducing the risk of parasitic breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a known oxide etch recipe is used to etch the silicon compound material layer, then the etching process is simple and fast, but the resulting silicon compound material layers along the sloped sidewall portion become rough and pitted
Solution Approach 1:
A preliminary action etch step is performed before the main etch process to create a smoother initial surface on the silicon compound material layer. This preliminary etching removes the rough outer layer and creates a more uniform surface that will result in smoother sidewalls after the complete etching process, thereby reducing metal trapping sites while maintaining etching efficiency
Solution Approach 2:
The etch recipe parameters are modified to optimize the balance between etching speed and sidewall smoothness. This includes adjusting etch chemistry composition, temperature, pressure, and power parameters to achieve a regime where the etching rate is maintained while the sidewall roughness is significantly reduced, preventing metal particle trapping
2Device complexity
If the sloped sidewall portion is left rough and pitted, then no additional processing steps are needed, but metal particles become trapped causing parasitic breakdown
Solution Approach 1:
A preliminary smoothing etch step is introduced early in the process sequence to create smooth sidewalls before metal deposition occurs. This preliminary action prevents metal particles from being trapped in rough surfaces, thereby improving reliability without adding complex post-processing steps or new materials
Solution Approach 2:
The rough, pitted sidewall surface that would normally trap metal particles is transformed into a smooth surface through the modified etch process. By converting the harmful roughness into a beneficial smooth surface, the process eliminates metal trapping sites and prevents parasitic breakdown while maintaining the original process flow
3Reliability
If two or more lower voltage capacitors are coupled in series to achieve extra-high voltage capacitance, then the voltage rating is increased, but additional silicon area is required
Solution Approach 1:
The breakdown voltage parameter of a single capacitor is increased by optimizing the dielectric layer thickness and composition, and by ensuring smooth sidewalls that prevent premature breakdown. This allows a single capacitor to achieve extra-high voltage ratings that previously required series-connected capacitors, thereby reducing the silicon area while maintaining the required voltage rating
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the roughness of the dielectric sidewall by up to 70%, minimizing the risk of premature breakdown and enabling the integration of high voltage capacitors with increased capacitance values within standard semiconductor processes, thus addressing the need for compact and reliable high voltage isolation solutions.
Implementation Method 1
sub-atmospheric chemical vapor deposition (SACVD) to fill the pores in the sloped sidewall portion
Implementation Method 2
high density plasma (HDP) to fill the pores in the sloped sidewall portion
Data Source
AI summary
An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.