Flash Memory Stack Structure With Stepped Cap Layer Sidewalls
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Solution Overview
Problem
In the conventional manufacturing process of flash memory devices, protruding portions at the corners of the gate structure can cause damage to the protective layer during etching, leading to element current leakage and reduced reliability.
Innovation Solution
The memory device features multiple stack structures with a cap layer having a multilayer structure, where the widths of the charge storage structure, control gate, and cap layer are equal, ensuring flat and smooth sidewalls, and a protective layer is formed to prevent damage during etching, with the cap layer serving as a polishing buffer for direct isolation of dummy source contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory manufacturing process is used, then production efficiency is maintained, but protruding portions are formed at corners above gate leading to protective layer damage and element current leakage
Solution Approach 1:
The cap layer is divided into multiple sub-layers (first cap layer and second cap layer) with different widths. The first cap layer has the same width as the control gate, while the second cap layer has a larger width, creating a stepped structure that eliminates protruding portions at corners.
Solution Approach 2:
Different regions of the cap layer are given different widths to serve specific functions. The first cap layer region aligns with the control gate for proper electrical isolation, while the second cap layer region extends wider to prevent protruding portions and protect the protective layer during etching processes.
2Reliability
If cap layer width is increased to prevent protruding portions, then protective layer protection is improved, but device dimensions increase
Solution Approach 1:
The cap layer is segmented into two distinct width regions. The first cap layer maintains the same width as the control gate, minimizing area usage, while the second cap layer extends wider only where needed to prevent protruding portions and protect the protective layer.
Solution Approach 2:
The cap layer width is locally optimized - narrower regions are used where precise alignment with the control gate is needed, while wider regions are used only where protection from protruding portions is required, thus minimizing overall area increase.
Data Source
AI summary
A memory device including a substrate, a plurality of stack structures, and a protective layer is provided. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In a cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, a width of the control gate, and a width of the cap layer are substantially equal to each other.