Vertical Semiconductor Device Dual Data Storage Structures
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently storing and reading multiple bits of data in a single memory cell, leading to increased complexity and reduced storage capacity due to the need for numerous states to distinguish between data bits.
Innovation Solution
A vertical semiconductor device design featuring a channel with stacked gate patterns and dual data storage structures, where the first data storage structure uses variable resistance materials and the second uses charge storage layers, allowing for independent data storage and reading mechanisms, thereby reducing the number of states required for multi-bit data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored in a single memory cell using conventional methods, then storage capacity increases, but the number of states required increases leading to increased complexity and reduced reliability
Solution Approach 1:
The patent divides a single memory cell into two independent data storage structures: a first data storage structure and a second data storage structure. Each structure independently stores one bit of data, eliminating the need for multiple states within a single storage element. This segmentation reduces complexity while maintaining multi-bit storage capacity.
Solution Approach 2:
The patent introduces a channel as an intermediary element that couples the first and second data storage structures. The channel enables independent access and reading of data from each storage structure through controlled charge transfer, allowing multi-bit storage without requiring the memory cell to exist in multiple simultaneous states.
2Quantity of substance
If multiple bits are stored in a single memory cell, then storage density increases, but reading accuracy decreases due to difficulty in distinguishing data bits
Solution Approach 1:
By segmenting the memory cell into two independent data storage structures, each structure stores one bit independently. This allows the reading operation to distinguish between data bits by selectively accessing each storage structure through the channel, thereby maintaining high reading accuracy while achieving multi-bit storage density.
Solution Approach 2:
The patent uses distinct physical mechanisms for data representation in the two storage structures: the first data storage structure uses variable resistance (analogous to different resistance 'colors'), and the second uses charge storage (analogous to different charge 'colors'). These distinct physical states enable clear differentiation and accurate reading of multiple data bits.
3Quantity of substance
If conventional multi-bit storage methods are used, then storage capacity increases, but the device requires numerous states leading to increased complexity
Solution Approach 1:
The memory cell is segmented into two independent data storage structures, each capable of storing one bit. This segmentation allows the system to achieve 2-bit storage capacity without requiring four states in a single storage element, thereby reducing device complexity while maintaining storage capacity.
Solution Approach 2:
The patent transitions from storing multiple bits within a single storage element (one-dimensional state multiplication) to using two separate storage structures (two-dimensional spatial expansion). This dimensional change allows multi-bit storage with fewer states per element, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient storage and reading of multiple bits in a single memory cell by utilizing the resistance levels of the first data storage structure and threshold voltage levels of the second, significantly reducing the number of states needed and enhancing data distinction and retrieval.
Implementation Method 1
the first data storage structure uses variable resistance materials
Implementation Method 2
the second uses charge storage layers
Data Source
AI summary
A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.