3D NAND Memory Charge Trapping Layer Removal for Select Gate Reliability
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming vertical stacks of multilevel memory arrays with precise control over dielectric layers and semiconductor channels, leading to suboptimal storage capacity and reliability.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers over a substrate, with specific processing steps to create memory openings, implant dopant atoms, and form tunneling and blocking dielectric layers, enabling the construction of a vertical semiconductor channel and charge trapping layers within the memory film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a charge trapping layer is included in the gate dielectric stack for top select gate electrode, then storage capacity is improved, but reliability deteriorates due to charge trapping effects
Solution Approach 1:
The gate dielectric stack is segmented into distinct functional layers: a blocking dielectric layer (first dielectric material) and a tunneling dielectric layer (second dielectric material). This segmentation allows each layer to perform its specific function - the blocking layer prevents charge trapping at the interface with the top select gate electrode, while the tunneling layer enables charge injection into the memory stack, thereby resolving the contradiction between storage capacity and reliability
Solution Approach 2:
Different dielectric materials are used at different locations within the gate dielectric stack to optimize local properties. The blocking dielectric layer is positioned adjacent to the top select gate electrode where charge blocking is needed, while the tunneling dielectric layer is positioned where charge injection is required. This local differentiation of material properties eliminates harmful charge trapping while preserving storage functionality
2Manufacturing precision
If multiple dielectric layers are formed with precise thickness control, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The charge trapping layer is extracted (removed) from the gate dielectric stack adjacent to the top select gate electrode. This extraction eliminates the source of charge trapping problems while maintaining the essential tunneling and blocking functions through the remaining dielectric layers, thereby reducing device complexity without sacrificing manufacturing precision
Solution Approach 2:
The gate dielectric stack uses composite dielectric materials with different properties - a blocking dielectric material and a tunneling dielectric material - arranged in specific layers. This composite structure achieves the desired electrical characteristics (charge blocking and tunneling) through material composition rather than complex multi-layer architectures, simplifying the overall device structure while maintaining manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of reliable and efficient three-dimensional NAND string memory devices with improved storage capacity and reduced complexity in device structure, enhancing the stability and performance of memory operations.
Implementation Method 1
Dopant atoms are implanted into an upper portion of the charge trapping layer
Implementation Method 2
an upper portion of a tunneling dielectric layer in physical contact with the upper portion of the blocking dielectric layer
Data Source
AI summary
A portion of a charge trapping layer adjacent to a select drain gate electrode can be removed employing a differential-rate etch process that provides an accelerated etch rate to a doped portion with respect to an undoped portion. If a silicon nitride layer is employed as the charge trapping layer, then angled ion implantation of boron atoms to an upper portion of the silicon nitride layer can increase the etch rate of the boron-doped portion of the silicon nitride layer in phosphoric acid. The charge trapping layer is etched back such that a remaining portion of the charge trapping layer can be present only at levels of control gate electrodes, and absent at each level of select drain gate electrodes. Threshold voltage shift for the select drain gate electrodes can be eliminated or reduced by removal of the charge trapping layer at each level of the select drain gate electrodes.