3D Memory Hole Structure With Tapered Diameter Control
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Solution Overview
Problem
In three-dimensional memory devices, high aspect ratio memory holes with varying diameters lead to inconsistent memory cell characteristics due to difficulties in controlling hole diameters uniformly, resulting in variations in electric field strengths across memory cells, causing erroneous writing and reading.
Innovation Solution
The semiconductor device incorporates a stacked body with columnar parts having distinct diameter portions, where the first portion has a larger diameter and the second portion has a smaller diameter, with corresponding electrode layers and insulating films, allowing for a convex-shaped semiconductor part and a thicker tunnel insulating part to manage electric fields effectively, thereby improving writing and deletion characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If anisotropic dry etching is used to form memory holes with high aspect ratios, then the memory device achieves higher integration density, but the diameter uniformity of memory holes deteriorates
Solution Approach 1:
The patent applies local quality by creating a tapered etch profile where the memory hole diameter varies along its depth. The upper portion has a larger diameter while the lower portion has a smaller diameter, optimizing each section for its specific function. This local variation in geometry resolves the contradiction by maintaining diameter control where critical while achieving high aspect ratios for density.
Solution Approach 2:
The patent changes the geometric parameter of the memory hole from a uniform cylinder to a tapered structure with varying diameter along the depth direction. This parameter change allows the upper portion to accommodate electrode layers properly while the lower portion maintains structural integrity, achieving both high integration density and acceptable diameter uniformity in critical regions.
2Length of stationary object
If memory holes with high aspect ratios are formed, then vertical space utilization is improved, but control of diameter uniformity in the depth direction becomes difficult
Solution Approach 1:
The tapered structure applies local quality by differentiating the diameter along the vertical axis. The upper portion with larger diameter optimizes space utilization and electrode layer accommodation, while the lower portion with smaller diameter maintains manufacturing control and structural stability, resolving the contradiction between vertical utilization and diameter control.
Solution Approach 2:
The patent transitions from a two-dimensional uniform cross-section to a three-dimensional tapered structure. This dimensional change allows optimization of both vertical space utilization and lateral diameter control by varying the radius as a function of depth, achieving high aspect ratios while maintaining precision where needed.
3Reliability
If uniform diameter memory holes are formed, then memory cell characteristic consistency is improved, but the aspect ratio must be reduced
Solution Approach 1:
The tapered structure applies local quality by creating different diameter zones. The upper portion with larger diameter ensures consistent electrode layer formation and memory cell characteristics, while the overall high aspect ratio is maintained through the reduced lower portion, resolving the contradiction between consistency and aspect ratio.
Solution Approach 2:
By changing the diameter parameter along the depth direction, the patent achieves both high aspect ratio and consistent memory cell characteristics. The controlled tapering ensures that critical dimensions at the upper portion remain uniform for consistent device performance while maximizing vertical integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures consistent electric field application across memory cells, reducing erroneous operations and enhancing reliability by addressing the variations in hole diameters and electric field strengths, thus improving the overall performance of the memory device.
Implementation Method 1
The memory holes are formed by e.g. anisotropic dry etching
Data Source
AI summary
A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape