Semiconductor Devices TRIZ Cases

A shared ohmic metal layer forms source, drain, and field plate to raise breakdown voltage while cutting mask steps.

Varying germanium content across source/drain regions and side-extending contacts cuts contact resistance and narrows pFET-nFET performance gaps.

A layered oxide-nitride trench insulator reduces edge electric field concentration, improves resin adhesion, and blocks moisture in high-voltage chips.

Ferroelectric and charge-trapping layers in a recessed III-V HEMT raise threshold voltage above 6V, enabling normally-off operation with lower power loss.

A deeper implanted well covers trench gate corners to reduce electric field concentration, raising breakdown voltage and lowering on-state resistance.

A layered GaN/AlGaN HEMT with a doped region and embedded gate boosts drive current while suppressing leakage current.

A recessed drift layer with tailored well, source, and JFET doping improves charge flow while keeping transistor capacitance low.

Microstructured prisms or reflectors in a cover recess redirect stray light away from the sensor, cutting noise, thickness, and blockage risk.

A raised base and dielectric spacer let the emitter overlap cleanly, enabling smaller-node BJT scaling with fewer process steps.

A semi-vertical GaN fin structure with p-type dielectric gates improves threshold stability, breakdown capability, and area use.

Staggered insulating-layer openings and a reflective conductive structure improve current spreading and light extraction for brighter LEDs.

A trench electrode with insulating films and field control spreads the electric field to prevent avalanche breakdown and snapback under high voltage.

A band-gap-engineered AlGaN/GaN channel and barrier structure controls 2D electron gas flow for stable high-temperature power conversion.

A conductive pattern and dielectric layer level cell and edge regions to reduce cracks and foreign substance ingress in power semiconductors.

Different barrier-height drain junctions improve hole injection in GaN HEMTs, reducing current collapse and dynamic on-state resistance.

Isolation regions inside the GaN HEMT active area suppress 2DEG formation to limit saturation current and improve short-circuit endurance.

Alternating ferroelectric and non-ferroelectric regions isolate adjacent 3D memory cells, reducing polarization disturbance and parasitic capacitance.

Guide walls steer photogenerated charges into the SPAD avalanche region, raising photon detection efficiency while lowering side diffusion and dark counts.

Nitride-based ferroelectric capacitors such as AlScN enable scaled FRAM with stable remnant polarization, near-zero wakeup, and fewer read disturbances.

An encapsulated lead-frame light module replaces PCB assemblies to cut solder joints, shrink package size, and improve reliability.

Anchoring structures on LED package recess sidewalls increase encapsulant contact area to resist delamination and moisture ingress.

Disconnected gate lines and insulation layers prevent opposite-polarity contact in back-contact solar cells while lowering resistance and cost.

Nitrogen-doped diamond and reflective electrodes improve carrier generation, enabling high-power photoconductive switching with low absorption.

A protection film fills grid-line gaps between stacked sheets to block process-gas wrap-around plating and keep passivation uniform.

A dielectric layer placed beneath GAA nanostructures cuts gate-to-substrate parasitic capacitance while supporting scaled multi-patterning.

Multiple hole injection regions under the drain capture trapped electrons, suppressing current collapse and expanding current paths in GaN transistors.

Roughened substrate sidewalls and tuned p-layer thickness boost UV output while widening light extraction beyond axial emission.

Differential oxide thickness and nitriding in trench structures lower DRAM gate induced drain leakage while preserving turn-on current.

A pillar-based photonic crystal opens a TM band gap in deep UV LEDs, cutting p-GaN absorption losses and boosting light extraction.

A pre-pattern nucleation layer enables selective III-nitride growth on patterned substrates, boosting LED brightness and narrow-cone emission.

An intermediate nitride layer blocks p-type impurity diffusion from the tunnel junction, preserving crystal quality and light output.

An undercut overhang structure links the OLED cathode to an auxiliary electrode to cut resistance, suppress VSS rise, and reduce luminance non-uniformity.

A source trench sized below 20% of the unit area shields gate trench corners from high electric fields while keeping on-resistance low.

Gradient via diameters, pitches, and electrode widths improve current spreading, recombination uniformity, and LED emission efficiency.

A container-shaped bottom electrode and reinforced corner dielectric raise capacitance while limiting leakage and parasitic capacitance.

A container-shaped bottom electrode preserves wider lower dimensions to raise capacitance while dielectric corner coverage helps prevent leakage.

Asymmetrical control gate strap projections improve contact formation in flash memory arrays while supporting data retention and simpler fabrication.

Separated vertical contacts and dielectric isolation connect non-adjacent FinFET epitaxial regions while supporting denser layouts.

A vertical channel gate stack uses ferroelectric and insulating layers to raise FeRAM density while limiting gate disturbance and preserving data retention.

A closed-loop spacer separates the protective layer from filler impact while the sealing member bonds directly to the substrates for stronger adhesion.

A necked dummy gate slows etch-back in replacement metal gate processing, keeping FinFET gate heights uniform and reducing shorts.

A protruding field dispersion layer and channel suppression region stabilize electric fields, cut leakage current, and raise breakdown voltage.

Inner dielectric and outer conductive spacers self-align gate metal, protect p-GaN gate edges, and cut channel resistance in GaN devices.

Inner dielectric spacers self-align gate metal in HEMTs, removing etch-back steps while reducing shorts, stress, time, and cost.

A backside grid electrode lets reflected light enter the silicon lower cell, raising current and conversion efficiency in a silicon-perovskite tandem solar cell.

Tailored buried layers, n-wells, p-wells, and p-type slots raise LDMOS breakdown voltage from about 90V to 150V.

A translucent substrate and reflective die attach reduce light absorption in vertical LED arrays, boosting output up to 20%.

Lower-barrier resonant tunneling layers improve electron injection in charge-trap memory, boosting switching speed with lower power use.

Dual dielectric spacers protect p-GaN gate edges and control field-plate alignment, enabling shorter GaN HEMT channels with lower resistance.