Container Electrode Memory Capacitor With Corner Leakage Control
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Solution Overview
Problem
Conventional etching techniques for high-aspect-ratio capacitors in memory devices result in reduced capacitance due to smaller dimensions at the bottom of the recess, leading to poor device performance and material loss, and wet etch techniques cause device defects.
Innovation Solution
A memory device design with a container-shaped bottom electrode and a dielectric structure that includes a dielectric layer and dielectric portions covering top corners, along with a top electrode structure, is fabricated using a method involving multiple support layers and dry etching to enhance capacitance and prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used for high-aspect-ratio capacitors, then the fabrication process is simple, but the capacitance is reduced due to smaller dimensions at the bottom of the recess
Solution Approach 1:
The etching process is divided into multiple stages: forming the container-shaped bottom electrode with wider base, then adding dielectric layers and top electrode structure in sequential steps. This segmentation allows each stage to be optimized independently, achieving high capacitance without requiring excessively complex single-step etching
Solution Approach 2:
The patent transitions from traditional vertical high-aspect-ratio recesses to a container-shaped structure with a wider base dimension. By changing the geometric dimensioning approach, the bottom electrode achieves larger area for higher capacitance while maintaining manufacturability through standard fabrication processes
2Reliability
If conventional wet etch techniques are used, then the etching process is simple, but significant material loss and device defects occur due to poor control
Solution Approach 1:
The patent replaces conventional wet etching with a deposition-based approach using atomic layer deposition (ALD) to form dielectric layers and electrode structures. This substitution eliminates the uncontrolled material removal of wet etching, preventing material loss and device defects while maintaining manufacturing feasibility through precise thin-film deposition
Solution Approach 2:
The fabrication process changes from etching-based to deposition-based parameters. By using ALD with controlled deposition rates and thicknesses, the process achieves superior material control and reduced defects compared to wet etching, despite increased process steps
3Reliability
If the dielectric structure thickness is increased at top corners, then leakage current is prevented, but the manufacturing complexity increases
Solution Approach 1:
The dielectric structure implements local quality enhancement by specifically increasing thickness at top corners where leakage risks are highest. The container-shaped bottom electrode and targeted dielectric portions provide localized reinforcement without requiring uniform thickness increase throughout the entire structure, maintaining manufacturing efficiency
Solution Approach 2:
The container-shaped bottom electrode is formed in advance with a wider base dimension before subsequent dielectric layers are deposited. This preliminary action creates a geometric foundation that naturally supports increased dielectric thickness at critical locations, preventing leakage current without requiring complex post-processing
Data Source
AI summary
The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.