Inner And Outer Gate Spacers for Short-Channel GaN HEMTs
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Solution Overview
Problem
Existing semiconductor structures face challenges in scaling high-electron-mobility transistors (HEMTs) to very short lengths while minimizing channel resistance and reducing stress on the edges of the p-GaN gate structure during fabrication, particularly when operating voltage is reduced.
Innovation Solution
The implementation of inner and outer dielectric spacers surrounding the gate structure, which are self-aligned and protect the gate structure during fabrication processes, reducing stress and process variability, and allowing for precise control of spacing and alignment of field plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is scaled down to reduce device size, then the device footprint is reduced, but the channel resistance increases
Solution Approach 1:
The gate structure is segmented into multiple components: a central gate electrode, inner sidewall spacers surrounding the gate metal, and outer sidewall spacers on the passivation layer. This segmentation allows for optimized electric field distribution and reduced channel resistance even at short channel lengths
Solution Approach 2:
The inner sidewall spacers act as an intermediary structure between the gate metal and the outer sidewall spacers, providing stress relief and precise spacing control that enables short channel operation with minimized resistance
2Length of moving object
If the gate structure is scaled down, then the device size is reduced, but stress on the gate structure edges increases during fabrication
Solution Approach 1:
The inner sidewall spacers are formed beforehand to surround and protect the gate metal edges during subsequent fabrication processes, cushioning against stress and damage before it occurs
Solution Approach 2:
The inner sidewall spacers serve as a protective intermediary layer between the gate metal and the outer sidewall spacers, absorbing and distributing stress during fabrication processes
3Device complexity
If single sidewall spacers are used, then the structure is simpler, but spacing control and alignment precision are insufficient
Solution Approach 1:
The spacer system is divided into two distinct segments: inner sidewall spacers for precise gate metal spacing and outer sidewall spacers for field plate alignment, with each segment performing a specialized function that together achieve high manufacturing precision
Solution Approach 2:
Different regions of the spacer structure have different properties and functions: the inner sidewall spacers provide stress relief and precise spacing for the gate metal, while the outer sidewall spacers provide alignment references for field plates, with each region optimized for its specific purpose
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a device with inner and outer spacer structures and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a gate metal connecting to the gate structure; inner sidewall spacers contacting and surrounding the gate metal; a passivation layer on the inner sidewall spacers; and outer sidewall spacers on the passivation layer and adjacent to sides of the gate structure.