Container-Shaped Memory Capacitor Structure for Higher Capacitance
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Solution Overview
Problem
Conventional etching techniques for high-aspect-ratio capacitors in memory devices result in reduced capacitance due to smaller dimensions at the bottom of the recess, leading to poor device performance and material loss, and wet etch techniques cause device defects.
Innovation Solution
A memory device design featuring a container-shaped bottom electrode with a dielectric structure and top electrode, where the dielectric portions cover the top corners of a support layer, increasing the overall thickness and preventing leakage current, and a method involving sequential layer formation and dry etching to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used for high-aspect-ratio capacitors, then the capacitor structure can be formed, but the dimension at the bottom of the recess becomes smaller, reducing capacitance
Solution Approach 1:
Instead of forming a traditional recess structure where the bottom is narrower than the top, the patent inverts the approach by forming a container-shaped electrode where the bottom portion is wider than or equal to the top portion. This is achieved through selective etching that removes sacrificial layers, creating an inverted trapezoidal or cylindrical container shape that maintains larger dimensions at the bottom to preserve capacitance while still achieving high aspect ratio.
Solution Approach 2:
The container-shaped electrode structure nests within the support layers and dielectric structures. The bottom electrode is formed within a container shape defined by support layers, and the top electrode is formed within a container shape defined by dielectric structures. This nested arrangement allows the capacitor to achieve high aspect ratio while maintaining adequate dimensions for capacitance through the container geometry.
2Ease of manufacture
If conventional wet etch techniques are used, then etching can be performed, but significant material loss and device defects occur due to poor control
Solution Approach 1:
The patent introduces sacrificial layers (first and second sacrificial layers) as intermediaries that facilitate the formation of the container-shaped electrode. These sacrificial layers are deposited, patterned, and etched to define the container shape, and then selectively removed to form the final electrode structure. This intermediary approach provides better control over the etching process, reduces material loss, and minimizes device defects compared to direct conventional wet etching.
3Reliability
If the dielectric structure thickness is increased to prevent leakage current, then leakage prevention is improved, but the overall device complexity increases
Solution Approach 1:
The patent applies local quality by forming dielectric portions specifically at critical locations where leakage current is most likely to occur, such as at the corners and edges of the container-shaped electrode. Rather than uniformly increasing dielectric thickness throughout the entire structure, the dielectric portions are strategically placed to provide localized leakage prevention, thereby improving reliability without proportionally increasing overall device complexity.
Data Source
AI summary
The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.