Resonant Tunneling Charge-Trap Memory for Fast Low-Power Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory devices face challenges in achieving high integration with improved operation speed and reduced power consumption.
Innovation Solution
A semiconductor device is designed with a stack structure comprising a tunnel layer, a first and second resonant tunneling layer, a charge trap layer, and a blocking layer, utilizing a resonant tunneling injection method to inject electrons efficiently, thereby enhancing switching speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional tunneling methods are used in nonvolatile memory devices, then data storage is achieved, but operation speed is limited and power consumption is high
Solution Approach 1:
The patent changes the energy barrier parameter of the tunneling layer by introducing resonant tunneling layers with lower energy barriers. This allows electrons to tunnel through at lower voltages and faster speeds, simultaneously improving operation speed and reducing power consumption while maintaining data storage functionality
Solution Approach 2:
The patent uses a composite structure combining conventional tunneling layers with resonant tunneling layers made of specific materials (e.g., MoS2, WS2, WSe2, MoSe2). This composite approach leverages the quantum mechanical resonant tunneling effect to achieve high-speed electron injection with reduced energy consumption
2Quantity of substance
If high integration is pursued in nonvolatile memory devices, then storage capacity increases, but operation speed and power consumption face technical limitations
Solution Approach 1:
The patent applies local quality by implementing resonant tunneling layers at specific critical locations within the memory device structure (between the channel pattern and electrode). This localized application of advanced materials enables high-speed operation in the data injection path while maintaining overall device integration for high storage capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves high speed operation with low power consumption and improved endurance characteristics, enabling efficient electron injection and multiple level states in nonvolatile memory devices.
Implementation Method 1
at least one resonant tunneling layer disposed between the tunnel layer and the blocking layer, and including a material having a lower energy barrier than the tunnel layer and the blocking layer
Data Source
AI summary
A semiconductor device may include an electrode over a channel pattern. An information storage pattern may be disposed between the channel pattern and the electrode. The information storage pattern may include a tunnel layer adjacent to the channel pattern; a blocking layer adjacent to the electrode; a charge trap layer between the tunnel layer and the blocking layer; a first resonant tunneling layer disposed between the tunnel layer and the charge trap layer, and including a material having a lower energy barrier than the tunnel layer; and a second resonant tunneling layer disposed between the charge trap layer and the blocking layer, and including a material having a lower energy barrier than the charge trap layer.