Semi-Vertical GaN Transistor Fin Layout for Threshold Stability
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Solution Overview
Problem
Conventional GaN-based power transistor devices face inefficiencies in area utilization, dynamic instabilities of threshold voltage, and reliability issues due to lateral technology limitations and p-GaN gate approaches, with limited degrees of freedom for tuning and breakdown voltage.
Innovation Solution
A semi-vertical transistor device design combining lateral and vertical GaN technologies, featuring a fin structure extending vertically from a channel layer, dielectric material sandwiching the fin, and p-type dielectric layers for gate contacts, allowing for reduced dimensions, improved breakdown capabilities, and tunable threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lateral GaN technology is used with all contacts on the same surface, then device performance can be adjusted by changing lateral layout, but area utilization efficiency and RDSON are inferior compared to vertical technology
Solution Approach 1:
The patent transitions from purely lateral contact arrangement to a semi-vertical structure where the fin extends vertically from the channel layer through the barrier layer, with drain contacts positioned at different vertical levels. This dimensional change improves area utilization while maintaining the lateral adjustability advantage through modified lateral positioning of gate and source contacts.
2Reliability
If p-GaN gate approach with p-type doped GaN layer is used, then normally-off operation with positive threshold voltage is achieved, but dynamic instabilities of threshold voltage and gate reliability issues occur
Solution Approach 1:
The patent replaces the p-type doped GaN layer with a p-type doped dielectric material (such as p-type silicon oxide or p-type silicon nitride). This material substitution changes the physical and electrical parameters of the gate structure, eliminating the polarization charge accumulation issues that cause threshold voltage instability while maintaining the normally-off operation capability through appropriate doping concentrations and material properties.
3Ease of manufacture
If conventional lateral GaN transistor design is used, then manufacturing process is straightforward, but breakdown voltage is limited and degrees of freedom for tuning are few
Solution Approach 1:
The patent introduces a vertical fin structure that extends from the channel layer through the barrier layer, creating additional vertical space for electric field management. This semi-vertical architecture increases breakdown voltage by providing greater distance for voltage distribution while maintaining compatibility with existing lateral fabrication processes. The fin structure also adds degrees of freedom through controllable dimensions (height, width, doping) that enable independent optimization of electrical characteristics.
Solution Approach 2:
The patent embeds the fin structure within the existing layer stack, with the fin extending vertically through the barrier layer and being surrounded by p-type doped dielectric material on its sides. This nested configuration allows the fin to utilize the vertical space efficiently while being protected and electrically isolated by the surrounding dielectric, maximizing breakdown voltage without requiring complete process redesign.
4Ease of manufacture
If GaN on silicon epitaxial growth with nucleation and transition layers is used, then device fabrication is enabled, but defects and dislocations cause current collapse and dynamic RDSON effects
Solution Approach 1:
The patent extracts and removes the problematic nucleation and transition layers from the epitaxial growth stack, retaining only the essential buffer and channel layers. By eliminating the intermediate layers that introduce defects and dislocations, the device achieves better reliability and reduced current collapse while maintaining the ability to fabricate GaN on silicon substrates. The simplified structure reduces defect density without sacrificing manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semi-vertical design achieves reduced device dimensions, enhanced breakdown voltage, and increased reliability by leveraging vertical GaN technology, providing more degrees of freedom for threshold voltage tuning and improved electric field distribution.
Implementation Method 1
Due to the presence of spontaneous and piezoelectric polarization charge, a high density electron inversion layer is formed at the interface between the AlGaN barrier layer and the GaN channel layer
Implementation Method 2
Due to the presence of spontaneous and piezoelectric polarization charge, a high density electron inversion layer is formed at the interface between the AlGaN barrier layer and the GaN channel layer
Data Source
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AI summary
This disclosure relates to a transistor device, e.g. based on GaN, and a method for fabricating the transistor device. The transistor device has a semi-vertical design The transistor device comprises a buffer layer and a channel layer of first semiconductor material, and a barrier layer of second semiconductor material on the channel layer. Further, a fm structure of the first semiconductor material extending on the channel layer. The fm structure also extends from the channel layer through an opening in the barrier layer. Dielectric material is arranged on the barrier layer on opposite sides of the fin structure, and two gate contacts are embedded in the dielectric material on opposite sides of the fin structure. Two drain contacts are connected to the ends of a channel formed in the channel layer and a source contact is arranged on a top surface of the fm structure.