Vertical Ferroelectric-Insulator Gate Stack for Dense FeRAM Arrays

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in increasing integration density and improving operating characteristics and reliability, particularly in non-volatile memory devices like ferroelectric random access memory (FeRAM) devices.

Innovation Solution

The semiconductor device incorporates a vertical channel structure with a ferroelectric-insulator gate stack, featuring a gate electrode penetrating vertical semiconductor patterns, surrounded by a ferroelectric pattern and a gate insulating pattern, which enhances integration density and reliability by reducing disturbance between adjacent gate structures and improving electric field intensity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional planar gate structures are used, then manufacturing is simpler, but integration density is limited

Engineering Contradiction:

Improveintegration densityVSAvoidgate structure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from conventional planar (2D) gate structures to vertical (3D) channel structures with gates extending in the depth direction. This dimensional change allows multiple channels to be stacked vertically, significantly increasing integration density while maintaining manufacturability through established vertical processing techniques.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate structure is nested within the vertical channel, with the gate electrode positioned inside the semiconductor channel and surrounded by ferroelectric and insulating layers. This nested configuration enables efficient use of vertical space and allows multiple such structures to be closely packed, enhancing integration density.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If gate structures are placed closer to increase density, then integration density improves, but disturbance between adjacent gates increases

Engineering Contradiction:

Improveintegration densityVSAvoidgate structure disturbance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

A gate insulating pattern is introduced as an intermediary layer between adjacent gate structures and between the ferroelectric pattern and the vertical semiconductor patterns. This intermediary effectively shields and isolates the gate structures, preventing electrical disturbance and interference while allowing them to be positioned closer together for higher density.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into distinct functional layers: gate electrode, ferroelectric pattern, and gate insulating pattern. This segmentation allows each layer to perform its specific function independently, with the insulating layer providing electrical isolation that enables closer spacing of adjacent gates without increasing disturbance.

Inventive Principle:

Principle #1Segmentation

3Reliability

If ferroelectric pattern polarity is enhanced for better data retention, then non-volatile memory performance improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvedata retentionVSAvoidferroelectric pattern formation precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure uses a composite material approach with distinct ferroelectric and insulating layers, each optimized for its specific function. The ferroelectric layer provides data retention while the insulating layer provides isolation, allowing the ferroelectric material to be optimized for polarity enhancement without compromising manufacturing feasibility through the supportive insulating structure.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for higher integration density and improved operating characteristics and reliability by maintaining data retention even after power interruption, with enhanced ferroelectric pattern polarity and gate insulating pattern endurance.

Implementation Method 1

a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns

Methodology Applied

Scientific EffectFerroelectricity:

Implementation Method 2

a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns

Methodology Applied

Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS12402321B2Vertical channel semiconductor device with ferroelectric-insulator gate stack

Publication Date: 2025.08.26 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.