Lateral Diffused Semiconductor Structure for Higher LDMOS Breakdown Voltage

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Solution Overview

Problem

Existing LDMOS devices face challenges in achieving high breakdown voltage, which is a limiting factor for high power applications.

Innovation Solution

The LDMOS devices are configured with doped regions, including n-type buried layers, high voltage n-wells, p-type wells, and p-type slots, which are tailored to enhance breakdown voltage by optimizing junction configurations and reducing surface electric fields.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If conventional LDMOS device structure is used, then device simplicity is maintained, but breakdown voltage is limited to around 90V

Engineering Contradiction:

Improvebreakdown voltageVSAvoiddevice structure

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The device structure is segmented into multiple functional regions including n-type buried layer, high voltage n-well, p-type well, and p-type slot region. This segmentation allows each region to contribute specifically to breakdown voltage enhancement while maintaining manageable structural complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions are doped with specific impurity concentrations tailored to their local functions: n-type buried layer with 1E16-1E18 atoms/cm³, high voltage n-well with 1E15-1E17 atoms/cm³, p-type well with 1E16-1E18 atoms/cm³, and p-type slot region with 1E17-1E19 atoms/cm³. This local quality optimization maximizes breakdown voltage at each critical interface.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If process steps are reduced for simpler manufacturing, then manufacturing efficiency improves, but junction configuration optimization is compromised

Engineering Contradiction:

Improvemanufacturing processVSAvoidjunction configuration

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The n-type buried layer is formed first in the substrate before subsequent epitaxial growth and well formation steps. This preliminary action establishes the foundation for achieving the desired breakdown voltage of 150V or higher while providing a stable base for subsequent processing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Multiple doped regions are nested within each other: the n-type buried layer is nested in the substrate, the high voltage n-well is formed over the buried layer, the p-type well is formed in the n-well, and the p-type slot region is formed in the p-type well. This nesting approach achieves complex junction configurations through sequential processing.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS20250267891A1Lateral diffused semiconductor device and forming method thereof

Publication Date: 2025.08.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a p-type epitaxial layer over a substrate, a plurality of n-type wells in the p-type epitaxial layer, a p-type well interfacing a first one of the plurality of n-type wells, a first n-type buried layer in the substrate, a source region in the p-type well, a drain region in a second one of the plurality of n-type wells, and a gate structure laterally between the source region and the drain region. Each of the plurality of n-type wells has a bottom surface entirely in contact with the substrate. The p-type well overlaps with an entirety of the first n-type buried layer.