Outer Conductive Spacer Gate Structure for p-GaN Edge Stress Relief
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining the integrity and reducing stress on the edges of the p-GaN gate structure during fabrication processes, particularly when forming a gate metal, which can lead to shorts and process variations.
Innovation Solution
The implementation of inner dielectric spacers and outer conductive spacers, along with a field plate, provides a self-aligned structure that protects the gate structure and reduces stress, while also serving as a field plate connecting to the source, using methods such as atomic layer deposition (ALD) and photolithographic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate metal is formed directly on the gate structure, then electrical connection is achieved, but stress concentration and shorts occur at the gate structure edges
Solution Approach 1:
The gate region is segmented into multiple functional zones using inner dielectric spacers and outer conductive spacers. The inner spacers create a first region with gate metal directly on the gate structure, while outer spacers create a second region with gate metal on the passivation layer, separating the high-stress gate edge area from the metal deposition area.
Solution Approach 2:
Passivation layer serves as an intermediary material between the gate structure and the gate metal in the second region. This intermediate layer prevents direct contact at the gate edges, eliminating stress concentration and short circuit risks while still allowing electrical connection through the controlled structure.
2Productivity
If gate metal is formed close to the gate structure edges, then connection efficiency is improved, but alignment precision and stress control become difficult
Solution Approach 1:
The inner dielectric spacers are formed first to define the precise location where gate metal should contact the gate structure. This preliminary structuring establishes the alignment reference before metal deposition, ensuring that the gate metal is positioned accurately in the first region without requiring high-precision alignment during subsequent processing.
3Device complexity
If single-layer spacer structure is used, then device complexity is reduced, but stress protection and field plate functionality are insufficient
Solution Approach 1:
The outer conductive spacers serve multiple functions simultaneously: they act as structural elements defining the second region, provide stress protection to the gate structure edges, and function as a field plate connecting to the source. This multi-functionality reduces the need for separate components while enhancing device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables scalable enhancement mode devices with reduced channel resistance and minimized stress on the p-GaN gate structure, ensuring precise alignment and protection during fabrication, thereby enhancing the performance and reliability of GaN power technologies.
Implementation Method 1
using methods such as atomic layer deposition (ALD) and photolithographic processes
Implementation Method 2
using methods such as atomic layer deposition (ALD) and photolithographic processes
Data Source
Figure 1
Figure 2
Figure 3A~3C
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to devices with an outer conductive spacer and methods of manufacture. The structure includes: a gate structure; a gate metal connecting to the gate structure; inner spacers contacting and surrounding the gate metal; a passivation layer on the inner spacers; and outer conductive spacers on the passivation layer and adjacent to sides of the gate structure.