Power Semiconductor Edge Structure for Step Difference Relief

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Solution Overview

Problem

Power semiconductor devices face challenges in maintaining reliability due to significant step differences between the cell region and the edge region, which can lead to cracks and foreign substance ingress.

Innovation Solution

The design includes a conductive pattern with specific height configurations and a dielectric layer to level the upper surfaces of the cell and edge regions, reducing the step difference and enhancing structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the cell region and edge region are formed with different structures, then the device functionality is improved, but a step difference occurs between regions leading to cracks and foreign substance ingress

Engineering Contradiction:
Improvedevice functionalityVSAvoidcrack resistance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

An insulating pattern is introduced as an intermediary structure between the cell region and edge region. This insulating pattern fills the step difference created by different structures in the two regions, providing a transitional interface that prevents cracks and foreign substance ingress while allowing both regions to maintain their distinct functional characteristics

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The solution addresses the step difference not by modifying the horizontal structure but by introducing a vertical dimension approach - using the insulating pattern to fill and level the height difference between regions, creating a coplanar surface that eliminates the step difference while preserving the underlying structural differences needed for device functionality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the cell region and edge region are formed with different structures, then the device functionality is improved, but foreign substance ingress occurs due to step difference

Engineering Contradiction:
Improvedevice functionalityVSAvoidforeign substance ingress
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The insulating pattern serves as a protective intermediary that fills the step difference between regions, creating a barrier that prevents foreign substances from entering through the interface between the cell region and edge region, while allowing both regions to maintain their functional distinctiveness

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If a step difference exists between cell region and edge region, then device functionality is maintained, but reliability decreases due to cracks

Engineering Contradiction:
Improvedevice functionalityVSAvoidcrack resistance
Core Design Contradiction:
Adaptability or versatilityVSStrength

Solution Approach 1:

The insulating pattern acts as a stress-distributing intermediary that fills the step difference between regions, eliminating stress concentration points that would otherwise lead to crack formation, while preserving the structural differences necessary for device functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating pattern is placed in advance at the interface between regions to cushion and absorb mechanical stresses before they can accumulate and cause cracks, providing preventive protection while maintaining the functional structure

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250287640A1Power semiconductor devices
Publication Date: 2025.09.11 SAMSUNG ELECTRONICS CO LTD
  • US20250287640A1 patent drawing
  • US20250287640A1 patent drawing
  • US20250287640A1 patent drawing

AI summary

A power semiconductor device includes a substrate including a cell region and an edge region extending from the cell region, a drift layer of a first conductivity type on the substrate, a first well region of a second conductivity type disposed within the drift layer, a source region of the first conductivity type disposed within the first well region, an insulating liner on the drift layer, gate electrodes spaced apart from each other on the insulating liner, an insulating pattern in the edge region, a conductive pattern spaced apart from the gate electrodes and covering a portion of the insulating liner and further covering a portion of the insulating pattern, a dielectric layer covering the gate electrodes and the conductive pattern, a source electrode on the dielectric layer, and a source contact plug penetrating through the dielectric layer and connecting the source electrode and the source region.