GaN HEMT Isolation Region Layout for Short-Circuit Endurance
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Solution Overview
Problem
GaN HEMTs face challenges in short-circuit endurance due to hotspots near the gate and field plates, with existing protection methods like current or voltage sensing adding parasitic inductance and not being practical for GaN circuits, and monolithic integration facing practical challenges.
Innovation Solution
A III-nitride transistor with a segmented active gate and isolation regions within the active area to prevent two-dimensional carrier gas formation, reducing saturation current and enhancing short-circuit endurance by integrating protection circuits monolithically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current sensing is used for short-circuit protection, then short-circuit detection capability is improved, but parasitic inductance increases which negatively affects switching performance
Solution Approach 1:
The patent extracts the short-circuit protection function from external discrete circuits and integrates it directly into the GaN HEMT device structure through isolation regions. This eliminates the need for separate current sensing circuits and their associated parasitic inductance, while maintaining short-circuit detection and protection capabilities through the inherent device physics of the isolated regions.
Solution Approach 2:
The isolation regions act as intermediaries that provide intrinsic short-circuit protection by creating localized regions where the two-dimensional carrier gas is prevented from forming. These regions serve as built-in current limits without requiring external sensing circuits, thereby protecting against short-circuit conditions while avoiding added parasitic inductance.
2Reliability
If voltage sensing is used for short-circuit protection, then short-circuit detection capability is improved, but on-state losses increase due to stray inductance
Solution Approach 1:
The patent removes the need for external voltage sensing circuits by integrating short-circuit protection directly into the device structure through isolation regions. This eliminates the stray inductance associated with external sensing circuits and their connections, thereby reducing on-state losses while maintaining protection capability.
Solution Approach 2:
The GaN HEMT with isolation regions provides self-protection against short-circuit conditions through its inherent structure. The isolation regions automatically limit current during short-circuit events without requiring external sensing or control circuits, eliminating the energy losses associated with external protection circuitry.
3Reliability
If isolation regions are added to reduce saturation current, then short-circuit endurance is improved, but device area increases
Solution Approach 1:
The patent segments the active area of the GaN HEMT by introducing isolation regions that divide the continuous two-dimensional carrier gas into isolated sections. This segmentation reduces the total saturation current by limiting the effective gate perimeter while maintaining the overall device area through efficient spatial arrangement of the isolated regions.
Solution Approach 2:
The isolation regions create local variations in the device structure where the two-dimensional carrier gas is prevented from forming in specific localized areas. This allows the majority of the device area to remain active and efficient while only the isolated regions modify the current characteristics, thereby improving short-circuit endurance without proportionally increasing the total device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The transistor exhibits lower saturation current and improved short-circuit endurance, allowing for better thermal dissipation and reduced on-state losses, with enhanced reverse conduction and transient performance.
Implementation Method 1
a heterojunction formed between two III-nitride semiconductor layers, the heterojunction being configured to allow the formation of a two-dimensional carrier gas (e.g. a two-dimensional electron gas, 2DEG)
Implementation Method 2
the piezopolarization charge present at the AlGaN/GaN heterostructure, results in a high electron density in the 2DEG layer
Data Source
AI summary
Described herein is a power transistor comprising: a source terminal; a drain terminal; a gate terminal; a heterojunction formed between two III-nitride semiconductor layers, the heterojunction being configured to allow the formation of a two-dimensional carrier gas at the heterojunction and thereby define an active area of the power transistor; and a plurality of isolation regions located inside a boundary of the active area, the plurality of isolation regions being configured to prevent the formation of the two-dimensional carrier gas inside the plurality of isolation regions; wherein the source terminal, the drain terminal, and the gate terminal are laterally spaced apart in a first direction, the gate terminal being located between the source terminal and the drain terminal; and wherein the isolation regions are laterally spaced apart from one another in a second direction, perpendicular to the first direction.