Semiconductor structure and method for manufacturing the same
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they are not entirely satisfactory in all aspects, particularly in reducing parasitic capacitance between the gate structure and the substrate, which affects the performance of GAA transistors.
Innovation Solution
The implementation of a dielectric layer between the nanostructures and the substrate in GAA transistors, combined with double-patterning or multi-patterning processes, to reduce parasitic capacitance and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional manufacturing methods are used for GAA devices, then the manufacturing process is simpler, but parasitic capacitance between the gate structure and substrate increases
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the gate structure and the substrate. This dielectric layer acts as a mediator that reduces parasitic capacitance by providing electrical isolation, thereby resolving the harmful electrostatic coupling without fundamentally changing the manufacturing process complexity
Solution Approach 2:
The patent introduces a vertical dimension by adding a dielectric layer in the Z-direction between the gate and substrate. This dimensional approach separates the gate structure from the substrate in the vertical axis, reducing parasitic capacitance while maintaining the existing lateral manufacturing processes
2Area of moving object
If GAA devices are scaled down to smaller technology nodes, then chip footprint is reduced, but manufacturing challenges increase
Solution Approach 1:
The manufacturing process is segmented into multiple patterning steps (double-patterning or multi-patterning). This segmentation allows the fabrication of smaller features by breaking down the pattern formation into sequential steps, thereby enabling reduced chip footprint while managing the increased manufacturing complexity through systematic process division
3Reliability
If dielectric layer is added between nanostructures and substrate, then parasitic capacitance is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The dielectric layer is formed as a preliminary step before final gate structure assembly. By preparing the dielectric isolation layer in advance, the subsequent gate fabrication steps are simplified, and the overall structure achieves reduced parasitic capacitance without excessive complexity in the final assembly process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of GAA transistors by reducing parasitic capacitance, thereby improving the functionality and efficiency of semiconductor structures.
Implementation Method 1
reduce parasitic capacitance between the gate structure and the substrate
Implementation Method 2
The dielectric layer is between and in contact with the nanostructures and the substrate in the Z-direction
Data Source
AI summary
A semiconductor structure includes a substrate, nanostructures, a dielectric layer, source/drain features, a gate structure, and inner spacers. The nanostructures are over the substrate and spaced apart from each other in a Z-direction. The dielectric layer is between and in contact with the nanostructures and the substrate in the Z-direction. The source/drain features are electrically connected to and on opposite sides of the nanostructures in an X-direction. The gate structure extends in a Y-direction and wraps around the nanostructures. The inner spacers are between the nanostructures and the substrate in the Z-direction. The inner spacers are on opposite sides of the dielectric layer in the X-direction.