Trench Oxide Nitriding Layout for Lower DRAM GIDL
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Solution Overview
Problem
The increasing integration of dynamic random access memory (DRAM) leads to smaller word line widths and trench sizes, resulting in gate induced drain leakage and reduced signal resolution, which affects performance and storage speed.
Innovation Solution
A method involving a deposition process to create a first oxide portion with greater thickness on the side walls of trench structures and a second oxide portion with lesser thickness on the bottom walls, combined with nitriding treatment to adjust nitrogen ion concentrations, ensuring a lower dielectric constant for the first oxide portion compared to the second, thereby reducing gate induced drain leakage and improving turn-on current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the structure size of the transistor is reduced to increase integration, then the integration density is improved, but gate induced drain leakage increases and performance deteriorates
Solution Approach 1:
The patent applies local quality by creating different oxide regions with distinct properties: a first oxide region with lower dielectric constant near the drain to reduce GIDL, and a second oxide region with higher dielectric constant away from the drain to maintain signal resolution. This spatial differentiation of material properties allows simultaneous achievement of high integration density and reduced leakage.
Solution Approach 2:
The patent changes the dielectric constant parameter of the oxide layer by introducing nitrogen ions at varying concentrations across different regions. The nitrogen ion concentration is higher in the first oxide region near the drain junction to reduce GIDL, and lower in the second oxide region away from the drain to maintain signal resolution, thus optimizing both integration density and reliability.
2Reliability
If the oxide layer thickness is increased to reduce leakage, then gate induced drain leakage is reduced, but turn-on current decreases
Solution Approach 1:
The patent applies local quality by creating a non-uniform oxide structure where the first oxide region near the drain has properties optimized for leakage reduction, while the second oxide region away from the drain has properties optimized for signal resolution. This localized differentiation allows the structure to reduce GIDL without sacrificing turn-on current.
Solution Approach 2:
The patent uses composite materials by combining oxide regions with different dielectric constants and nitrogen ion concentrations. The first oxide region contains higher nitrogen concentration for leakage reduction, while the second oxide region has lower nitrogen concentration for maintaining turn-on current, creating a composite structure that optimizes both parameters simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes gate induced drain leakage and enhances the sensitivity and performance of the semiconductor structure by ensuring efficient electron transfer and reducing leakage at junctions, while maintaining high turn-on current.
Implementation Method 1
by means of a deposition process, the thickness of a first oxide portion covering side walls of each of the trench structures is greater than the thickness of a second oxide portion covering bottom walls of each of the trench structures
Implementation Method 2
by means of nitriding treatment, the concentration of nitrogen ions in the first oxide portion is less than the concentration of nitrogen ions in the second oxide portion
Implementation Method 3
the concentration of nitrogen ions in the first oxide portion is less than the concentration of nitrogen ions in the second oxide portion
Data Source
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AI summary
The present application relates to the technical field of semiconductors, and provides a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate with trench structures; forming a source region and a drain region respectively on both sides of each of the trench structures; forming an oxide layer, the oxide layer including a first oxide portion covering side walls of each of the trench structured and a second oxide portion covering a bottom wall of each of the trench structures, and a thickness of the second oxide portion being less than a thickness of the first oxide portion; and nitriding the oxide layer, so that a concentration of nitrogen ions in the first oxide portion is less than a concentration of nitrogen ions in the second oxide portion. In the present application, the thickness of the first oxide portion is greater than the thickness of the second oxide portion and the concentration of nitrogen ions in the first oxide portion is less than the concentration of nitrogen ions in the second oxide portion, so that dielectric constant of the first oxide portion is less than dielectric constant of the second oxide portion. In this way, gate induced drain leakage can be reduced, and turn-on current sensitivity of the semiconductor structure can also be improved.