3D Memory Insulating Layer Polishing to Remove Residues

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Solution Overview

Problem

In the manufacturing of three-dimensional memory devices, the formation of insulating layers with depressions on the surface can lead to material residues, which pose hidden dangers and interfere with subsequent processes, particularly due to the deposition of materials like polysilicon that can fill or remain in these depressions.

Innovation Solution

A method is introduced where an insulating layer is formed on the surface of a stacked structure with grooves, and then polished to flatten the depression, thereby eliminating material residues and ensuring a flat surface, reducing the risk of residual material interference in subsequent processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If an insulating layer is formed in a groove of the gate line slit region, then the groove is filled and the stacked structure is stabilized, but a depression is created on the surface of the insulating layer which can trap material residues

Engineering Contradiction:
Improvestability of stacked structureVSAvoidmaterial residues in depression
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

A planarization layer is formed in advance to cover and flatten the depression on the insulating layer surface before subsequent material deposition processes. This preliminary action prevents material residues from being trapped in the depression during later manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The depression containing material residues is removed by forming a new planarization layer that replaces the defective insulating layer surface. The problematic depression structure is extracted and replaced with a flat surface through the additional planarization step.

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If the insulating layer surface with depression is used directly, then the manufacturing process is simpler, but material residues interfere with subsequent processes

Engineering Contradiction:
Improveease of insulating layer formationVSAvoidreliability of subsequent processes
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A planarization layer is deposited in advance to create a flat surface before subsequent material deposition. This preliminary planarization ensures that no material residues are trapped, maintaining reliability of subsequent processes while adding only one straightforward deposition step.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If polysilicon is deposited on the insulating layer with depression, then the depression fills with polysilicon residues, but this creates hidden dangers for device performance

Engineering Contradiction:
Improvepolysilicon depositionVSAvoidpolysilicon residues in depression
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The planarization layer is formed before polysilicon deposition to eliminate the depression. This ensures that polysilicon is deposited uniformly on a flat surface without accumulating in depressions, preventing harmful residues while maintaining the necessary polysilicon quantity for device function.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the stability of the stacked structure by preventing material residues from falling off or interfering with current processes, improving the reliability and efficiency of the manufacturing process for three-dimensional memory devices.

Implementation Method 1

The insulating layer is polished to flatten the depression

Methodology Applied
Scientific EffectMechanical polishing: Abrasion

Data Source

PatentUS20230114522A1Three-dimensional memory device and method for manufacturing three-dimensional memory device
Publication Date: 2023.04.13 YANGTZE MEMORY TECH CO LTD
  • US20230114522A1 patent drawing
  • US20230114522A1 patent drawing
  • US20230114522A1 patent drawing

AI summary

A three-dimensional memory device and a method for manufacturing the same are provided. The method includes steps as follows. A semiconductor structure including a substrate and a stacked structure on the substrate is provided. The stacked structure includes alternately stacked gate layers and dielectric layers, or alternately stacked dummy gate layers and dielectric layers. The dummy gate layers are replaceable by the gate layers. A groove is formed in a gate line slit region of the stacked structure. The groove penetrates through the gate layers and multiple layers of the dielectric layers, or through the dummy gate layers and multiple layers of the dielectric layers. An insulating layer is formed on a surface of the stacked structure and in the groove. A depression is formed on a surface of the insulating layer above the groove away from the substrate. The insulating layer is polished to flatten the depression.