Solid-State Devices TRIZ Cases

Lateral waveguide absorption extends the optical path length within thin silicon layers, resolving low responsivity and high capacitance in SOI CMOS processes.

A silicon on insulator combined semiconductor device merges PNP and N-type lateral insulated-gate bipolar transistors into a single integrated structure.

Asymmetric solder mask dam structures resolve auto-orientation detection difficulties caused by reduced chip offsets in modern packaging.

Selective masking isolates the channel region from metal-induced lateral crystallization fronts during semiconductor layer processing.

Sidewall dielectric layer protects LED epitaxy structure during laser substrate removal, preventing adhesive decomposition and peeling.

Segmented oxygen diffusion barriers isolate adjacent RRAM stacks, preventing inter-stack migration and stabilizing filament formation.

A two-step ion implantation process forms a delamination layer in bonded wafers to ensure precise film thickness.

A low profile side emitting LED integrates optical elements directly onto its sidewalls to redirect light efficiently.

A dielectric film on phase change memory electrodes reduces programming current by blocking heat propagation through the electrode structure.

A fluorine-rich interfacial layer forms between tungsten nucleation and filling layers to enhance polishing resistance during chemical mechanical processing.

Controlled Giant Surface Potential slope differences between stacked hole-transport layers reduce driving voltage and improve emission efficiency.

A protective layer shields memory region spacers during periphery processing to enable self-aligned contact formation.

A 3D semiconductor memory device uses a controller to apply specific voltages to shared well regions for pass transistor groups.

Penetrating ruts in pixel barriers isolate electrical paths, suppressing leaking light and short circuits while maintaining display resolution.

A multilayer composite bonding material with graded stiffness mitigates thermal contraction mismatch in power electronics assemblies.

A dual-gate oxide thin film transistor array substrate integrates polycrystalline silicon transistors to enhance carrier mobility and driving current.

A printed layer on a cover window matches display panel color and reflected luminance to unify the visual appearance of the bezel area.

Isotropic etching removes sacrificial layers to form backside trenches, enabling efficient integration of vertical NAND strings without complex spacer steps.

UV-curable oxetane-epoxy resin composition adheres strongly to flexible substrates, blocking moisture and oxygen from sensitive OLED organic layers.

Curved liquid crystal display light-shielding patterns adjust pitch and width to prevent light leakage and color mixing from non-monotonic misalignment.

An optical assembly uses a regular grid of luminescence diode chips to combine light into smaller unit cells.

Polishing insulating layer depressions in 3D memory stacks eliminates material residues that interfere with subsequent polysilicon deposition processes.

Patterned charge-trapping layer exposes distinct device areas for separate gate oxide formation, preventing substrate defects in low-voltage regions.

A transparent resin layer with a triangular cross-section guides visible light from a scintillator to photodetection elements, reducing crosstalk and noise.

Selective fluorine etching reduces jagged topography and sharp projections on semiconductor sidewalls, preventing defects in integrated circuits.

A semiconductor light emitting apparatus uses series-connected LEDs on a substrate to reduce electrical resistance and heat generation.

Increasing oxide semiconductor surface roughness via plasma treatment improves carrier mobility and power efficiency in display apparatuses.

A plasma-doped pinning layer passivates photodiode surface defects to improve charge transfer speed and sensitivity in miniaturized pixels.