Semiconductor Sidewall Smoothing via Selective Fluorine Etching
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Solution Overview
Problem
The formation of jagged topography during semiconductor processing, such as scalloping of sidewall peripheries, leads to defects like cracking and shorts in integrated circuits and sharp corners in semiconductor pedestals, which can cause reliability issues and affect the performance of structures like macrolens systems.
Innovation Solution
A selective etching process is employed to reduce the sharpness of features across the topography, specifically targeting the semiconductor material while maintaining high throughput, using a combination of gases like CF4, CHF3, and NF3, which selectively etches silicon dioxide relative to organic materials, thereby reducing the jaggedness of sidewalls and eliminating sharp projections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high etch rate is utilized to increase throughput, then productivity is improved, but manufacturing precision deteriorates due to increased scallop size and jagged topography
Solution Approach 1:
The etching process is divided into multiple sequential steps with different gas chemistries and parameters. The first etch step uses high power to achieve high etch rate and throughput, while subsequent steps use different gas compositions to smooth the sidewalls and remove scallops, thereby segmenting the conflicting requirements of speed and precision across different process stages
Solution Approach 2:
The patent changes multiple process parameters including gas composition (switching between CF4/CHF3/NF3 and other chemistries), power levels, and pressure conditions between etching steps. These parameter changes enable the system to achieve both high etch rates for throughput and smooth sidewalls for precision by optimizing conditions for each specific process objective
2Productivity
If conventional etching is used to form openings, then productivity is maintained, but reliability deteriorates due to cracking and defects from jagged topography
Solution Approach 1:
The patent performs preliminary sidewall smoothing and scallop removal etching steps before subsequent material deposition processes. This preliminary action eliminates the jagged topography that would otherwise cause cracking and defects during later processing, thereby ensuring reliability while maintaining overall productivity
Solution Approach 2:
The patent converts the harmful effect of high etch rate scalloping into a benefit by using the same high-power etching conditions to create initial openings, then following with controlled lower-power steps that specifically target and remove the scallops. The harmful scallop structure becomes the target for a specialized smoothing step that improves reliability
3Productivity
If high power is used during etching to increase etch rate, then productivity is improved, but manufacturing precision deteriorates due to increased scalloping
Solution Approach 1:
The patent employs periodic alternation between high-power etching pulses and low-power smoothing pulses. The high-power pulses provide rapid material removal for productivity, while the low-power pulses periodically smooth the sidewalls and reduce scalloping, creating a cyclical process that achieves both high average etch rate and good sidewall uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The etching process effectively alleviates jagged topography and sharp corners, reducing the risk of defects during material deposition and enhancing the reliability of semiconductor structures by smoothing sidewalls and preventing cracking, while maintaining high processing efficiency.
Implementation Method 1
A selective etching process is employed to reduce the sharpness of features across the topography, specifically targeting the semiconductor material while maintaining high throughput
Implementation Method 2
using a combination of gases like CF4, CHF3, and NF3, which selectively etches silicon dioxide relative to organic materials, thereby reducing the jaggedness of sidewalls and eliminating sharp projections
Data Source
AI summary
Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.