Spacerless Source Contact Layer Replacement in 3D Memory
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Solution Overview
Problem
Current three-dimensional memory device fabrication methods face challenges in efficiently forming spacerless source contact layers, which are crucial for the integration of vertical NAND strings, due to complexities in etching and replacing sacrificial layers without compromising device performance.
Innovation Solution
A spacerless source contact layer replacement process is developed, involving the formation of source-level material layers, alternating stacks of insulating and sacrificial layers, and isotropic etching to create backside trenches, allowing for the replacement of sacrificial layers with electrically conductive materials, thereby forming a planar and pillar source contact layer structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional spacer-based source contact layer formation is used, then source contact structure can be formed, but device complexity and manufacturing difficulty increase due to additional spacer formation and etching steps
Solution Approach 1:
The patent removes the spacer component entirely from the source contact layer formation process. By using a planarization layer instead of spacers to define the source contact regions, the method extracts and eliminates the complex spacer formation and removal steps, directly reducing device complexity and manufacturing difficulty.
Solution Approach 2:
Instead of forming source contact layers through spacer-defined etching (traditional approach), the patent inverts the approach by using a planarization layer deposited over the sacrificial layer, then removing portions of the planarization layer to expose the sacrificial layer, which is then replaced to form the source contact layer. This inverted sequence simplifies the overall process.
2Ease of manufacture
If isotropic etching is used to remove sacrificial layers and form backside trenches, then etching process is simplified, but lateral precision and pattern definition may be compromised
Solution Approach 1:
The patent performs preliminary patterning of the planarization layer before isotropic etching to define the source contact regions. By pre-defining the pattern in the planarization layer, the subsequent isotropic etch can proceed without requiring high lateral precision, as the pattern is already established by the planarization layer removal.
Solution Approach 2:
The planarization layer acts as an intermediary that defines the pattern before the isotropic etch process. This intermediary layer allows the use of simplified isotropic etching while maintaining manufacturing precision, as the planarization layer's pattern transfer provides the necessary definition during the etching process.
3Productivity
If source contact layer is formed without spacers, then manufacturing efficiency improves, but control over source contact dimensions and alignment becomes more challenging
Solution Approach 1:
The patent replaces the mechanical spacer-based dimensional control system with a deposition-based planarization layer system. The planarization layer's thickness and pattern, controlled through deposition processes, define the source contact dimensions and alignment, eliminating the need for mechanical spacer formation and removal while maintaining precision.
Solution Approach 2:
The patent changes the controlling parameter for source contact dimensions from spacer width (mechanical dimension) to planarization layer thickness and pattern (deposition parameter). This parameter change allows for better control through standardized thin-film deposition processes, improving both manufacturing efficiency and dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the efficient integration of source contact layers in three-dimensional memory devices, enhancing the structural integrity and performance of vertical NAND strings by eliminating the need for spacers and simplifying the etching process, leading to improved device reliability and manufacturing efficiency.
Implementation Method 1
forming a source cavity by removing the source-level sacrificial layer employing an isotropic etch process that provides an isotropic etchant into the backside openings
Data Source
AI summary
In-process source-level material layers including a source-level sacrificial layer is formed over a substrate, and an alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory openings and backside openings are formed through the alternating stack and into the in-process source-level material layers. Memory opening fill structures are formed in the memory openings. A source cavity is formed by removing the source-level sacrificial layer by introducing an etchant through the backside openings, and a source contact layer in the source cavity. The backside openings are laterally expanded and are merged to form backside trenches. Remaining portions of the sacrificial material layers are replaced with electrically conductive layers through the respective backside trenches.